ADC12L030 Datasheet, PDF (9/36 Pages) National Semiconductor (TI) – 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold

AC Electrical Characteristics (Continued)
The
sion
following
mode, t_r
specifications apply for
= t_f = 3 ns, f_CK = f_SK =
V⁺ = V_A+ =
5 MHz, R_S
=V^D25+Ω^=,
+3.3 V_DC, V_REF+ = +2.500 V_DC, V_REF− = 0 V_DC, 12-bit + sign conver-
source impedance for V_REF+ and V_REF− ≤ 25Ω, fully-differential input
with fixed 1.250V common-mode voltage, and 10(t_CK) acquisition time unless otherwise specified. Boldface limits apply for T_A
= T_J = T_MIN to T_MAX; all other limits T_A = T_J = 25˚C. (Note 17)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 10)
(Note 11)
(Limits)
t_SPU
Software Power-Up Time, Time from
Serial Data Clock Falling Edge to
500
700
µs (max)
EOC Rising Edge
t_ACC
Access Time Delay from
CS Falling Edge to DO Data Valid
25
60
ns (max)
t_SET-UP
Set-Up Time of CS Falling Edge to
Serial Data Clock Rising Edge
50
ns (min)
t_DELAY
Delay from SCLK Falling
Edge to CS Falling Edge
0
5
ns (min)
t_1H, t_0H
Delay from CS Rising Edge to
DO TRI-STATE
R_L = 3k, C_L = 100 pF
70
100
ns (max)
t_HDI
DI Hold Time from Serial Data
Clock Rising Edge
5
15
ns (min)
t_SDI
DI Set-Up Time from Serial Data
Clock Rising Edge
5
10
ns (min)
t_HDO
DO Hold Time from Serial Data
R_L = 3k, C_L = 100 pF
35
65
ns (max)
Clock Falling Edge
5
ns (min)
t_DDO
Delay from Serial Data Clock
Falling Edge to DO Data Valid
50
90
ns (max)
t_RDO
DO Rise Time, TRI-STATE to High
R_L = 3k, C_L = 100 pF
10
40
ns (max)
DO Rise Time, Low to High
10
40
ns (max)
t_FDO
DO Fall Time, TRI-STATE to Low
R_L = 3k, C_L = 100 pF
15
40
ns (max)
DO Fall Time, High to Low
15
40
ns (max)
t_CD
Delay from CS Falling Edge
to DOR Falling Edge
50
80
ns (max)
t_SD
Delay from Serial Data Clock Falling
Edge to DOR Rising Edge
45
80
ns (max)
C_IN
Capacitance of Logic Inputs
10
pF
C_OUT
Capacitance of Logic Outputs
20
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V_IN) at any pin exceeds the power supplies (V_IN < GND or V_IN > V_A+ or V_D+), the current at that pin should be limited to 20 mA.
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 20 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T_Jmax, θ_JA and the ambient temperature, T_A. The maximum
allowable power dissipation at any temperature is P_D = (T_Jmax − T_A)/θ_JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
T_J max = 150˚C. The typical thermal resistance (θ_JA) of these parts when board mounted follow:
9
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