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ADC12030_07 Datasheet, PDF (9/44 Pages) National Semiconductor (TI) – Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
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Parameter
tC
Conversion Time
Conditions
12-Bit + Sign or 12-Bit
8-Bit + Sign or 8-Bit
6 Cycles Programmed
10 Cycles Programmed
tA
Acquisition Time (Note 19)
18 Cycles Programmed
34 Cycles Programmed
tCKAL Self-Calibration Time
tAZ
Auto-Zero Time
tSYNC
Self-Calibration or Auto-Zero
Synchronization Time from
DOR
DOR High Time when CS is
tDOR
Low Continuously for Read
Data and Software Power Up/
Down
tCONV CONV Valid Data Time
Typical
(Note 10)
44(tCK)
21(tCK)
6(tCK)
10(tCK)
18(tCK)
34(tCK)
4944(tCK)
76(tCK)
2(tCK)
 
9(tSK)
ADC12H030/2/4/8 ADC12030/2/4/8
Limits
Limits
(Note 11)
(Note 11)
44(tCK)
5.5
44(tCK)
8.8
21(tCK)
2.625
21(tCK)
4.2
6(tCK)
7(tCK)
0.75
0.875
6(tCK)
7(tCK)
1.2
1.4
10(tCK)
11(tCK)
1.25
1.375
10(tCK)
11(tCK)
2.0
2.2
18(tCK)
19(tCK)
2.25
18(tCK)
19(tCK)
3.6
2.375
3.8
34(tCK)
35(tCK)
4.25
4.375
34(tCK)
35(tCK)
6.8
7.0
4944(tCK)
618.0
4944(tCK)
988.8
76(tCK)
9.5
76(tCK)
15.2
2(tCK)
3(tCK)
0.250
0.375
2(tCK)
3(tCK)
0.40
0.60
 
9(tSK)
1.125
 
9(tSK)
1.8
8(tSK)
8(tSK)
1.0
8(tSK)
1.6
Units
(Limits)
(max)
µs (max)
(max)
µs (max)
(min)
(max)
µs (min)
µs (max)
(min)
(max)
µs (min)
µs (max)
(min)
(max)
µs (min)
µs (max)
(min)
(max)
µs (min)
µs (max)
(max)
µs (max)
(max)
µs (max)
(min)
(max)
µs (min)
µs (max)
 
(max)
µs (max)
(max)
µs (max)
Timing Characteristics
The following specifications apply for V+ = VA+ = VD+ = +5.0 VDC, VREF+ = +4.096 VDC, VREF− = 0 VDC, 12-bit + sign conversion
mode, tr = tf = 3 ns, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H03, fCK = fSK = 5 MHz for the
ADC12030, ADC12032, ADC12034 and ADC12038, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential
input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for
TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (Note 17)
Symbol
Parameter
Conditions
Typical Limits
(Note 10) (Note 11)
Units
(Limits)
tHPU
Hardware Power-Up Time, Time from PD Falling Edge to
EOC Rising Edge
140
250
µs (max)
tSPU
Software Power-Up Time, Time from Serial Data Clock
Falling Edge to EOC Rising Edge
140
250
µs (max)
tACC
tSET-UP
Access Time Delay from CS Falling Edge to DO Data Valid
Set-Up Time of CS Falling Edge to Serial Data Clock Rising
Edge
20
50
ns (max)
30
ns (min)
9
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