ADC08B200 Datasheet, PDF (9/30 Pages) National Semiconductor (TI) – 8-Bit, 200 MSPS A/D Converter with Capture Buffer

Symbol
Parameter
t_AD
Sampling (Aperture) Delay
t_AJ
Aperture Jitter
Conditions
CLK Rise to
PLL on
Acquisition of Data PLL off
PLL Bypassed
PLL Enabled in x8 mode (Note 13)
Typical
(Note 9)
3.4
3.9
2
7
Limits
(Note 9)
Units
(Limits)
ns
ns
ps rms
ps rms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than GND or DR GND, or greater than V_A, V_P, V_D or V_DR), the current at that
pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by T_Jmax, the
junction-to-ambient thermal resistance (θ_JA), and the ambient temperature (T_A), and can be calculated using the formula P_DMAX = (T_Jmax − T_A) / θ_JA.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to V_A + 300 mV or to 300 mV below GND will not damage this device.
However, errors in the A/D conversion can occur if
must be ≤3.4V_DC to ensure accurate conversions.
the
input
goes
above
V_A
or
below
GND
by
more
than
100
mV.
For
example,
if
V_A
is
3.3V_DC
the
input
voltage
20214707
Note 8: To guarantee accuracy, it is required that V_A, V_D, V_P and V_DR be well bypassed. Each supply pin should be decoupled with separate bypass capacitors.
Note 9: Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
Level).
Note 10: This current or power is used only during the short time that the buffer is being written to or read from, depending upon the specification.
Note 11: This parameter is guaranteed by design and/or characterization and is not production tested.
Note 12: RCLK should be stopped with the buffer is not being read.
Note 13: Jitter with the PLL enabled is measured with 32k samples and the PLL in the x8 multiplication mode.
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