LP5550 Datasheet, PDF (8/25 Pages) National Semiconductor (TI) – PowerWise Technology Compliant Energy Management Unit

Logic and Control Inputs Unless otherwise noted, V_BAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values
and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8, 9) (Continued)
Symbol
R_{PD_PWI}
T_{EN_LOW}
Parameter
Pull-down resistance for PWI
signals
Minimum low pulse width to
enter STARTUP state
Conditions
ENABLE pulsed high - low - high
from SHUTDOWN state
ENABLE pulsed high - low - high
from SLEEP or ACTIVE state
Min
Typ Max Units
0.5
1
2 MΩ
100
µsec
4
Logic and Control Outputs Unless otherwise noted, V_BAT1,2,SW , RESETN, ENABLE = 3.6V. Typical val-
ues and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8, 9)
Symbol
V_OL
V_OH
V_{OH_PWI}
Parameter
Output low level
Output high level
Output high level, PWI
Conditions
Min
Typ
PWROK, SPWI, I_SINK ≤ 1 mA
PWROK, I_SOURCE ≤ 1 mA
SPWI, I_SOURCE ≤ 1 mA
V_BAT1-0.4V
V_O2-0.4V
Max Units
0.4 V
V
V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula P = (TJ
– TA)/θ_JA, (1) where TJ is the junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient thermal resistance.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care
must be paid to thermal dissipation issues in board design.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150˚C (typ.) and disengages at TJ=140˚C (typ.).
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package (LLP)
(AN-1187).
Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125˚C), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ_JA), as given by the
following equation: TA-MAX = TJ-MAX-OP – (θJA x PD-MAX).
Note 6: Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC
standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102mm x 76mm x 1.6mm with a 2x1 array of thermal vias. The ground plane on the board
is 50mm x 50mm. Thickness of copper layers are 36µm/18µm/18µm/36µm (1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22˚C, still air. Power
dissipation is 1W.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care
must be paid to thermal dissipation issues in board design.
The value of θ_JA of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In applications where high maximum power
dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application
Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet.
Note 7: All limits are guaranteed by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production
with TJ = 25C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process
control.
Note 8: Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics
Note 9: Guaranteed by design.
Note 10: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply
in cases it implies operation with an input voltage below the 3.0V minimum appearing under Operating Ratings. For example, this specification does not apply for
devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V
Note 11: Quiescent current for LDO1, LDO2, and LDO3 do not include shared functional blocks such as the bandgap reference.
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