LP38843 Datasheet, PDF (8/11 Pages) National Semiconductor (TI) – 3A Ultra Low Dropout Linear Regulators Stable with Ceramic Output Capacitors

Application Hints
EXTERNAL CAPACITORS
To assure regulator stability, input and output capacitors are
required as shown in the Typical Application Circuit.
OUTPUT CAPACITOR
An output capacitor is required on the LP3884X devices for
loop stability. The minimum value of capacitance necessary
depends on type of capacitor: if a solid Tantalum capacitor is
used, the part is stable with capacitor values as low as 4.7µF.
If a ceramic capacitor is used, a minimum of 22 µF of
capacitance must be used (capacitance may be increased
without limit). The reason a larger ceramic capacitor is re-
quired is that the output capacitor sets a pole which limits the
loop bandwidth. The Tantalum capacitor has a higher ESR
than the ceramic which provides more phase margin to the
loop, thereby allowing the use of a smaller output capacitor
because adequate phase margin can be maintained out to a
higher crossover frequency. The tantalum capacitor will typi-
cally also provide faster settling time on the output after a
fast changing load transient occurs, but the ceramic capaci-
tor is superior for bypassing high frequency noise.
The output capacitor must be located less than one centi-
meter from the output pin and returned to a clean analog
ground. Care must be taken in choosing the output capacitor
to ensure that sufficient capacitance is provided over the full
operating temperature range. If ceramics are selected, only
X7R or X5R types may be used because Z5U and Y5F types
suffer severe loss of capacitance with temperature and ap-
plied voltage and may only provide 20% of their rated ca-
pacitance in operation.
INPUT CAPACITOR
The input capacitor is also critical to loop stability because it
provides a low source impedance for the regulator. The
minimum required input capacitance is 10 µF ceramic (Tan-
talum not recommended). The value of C_IN may be in-
creased without limit. As stated above, X5R or X7R must be
used to ensure sufficient capacitance is provided. The input
capacitor must be located less than one centimeter from the
input pin and returned to a clean analog ground.
BIAS CAPACITOR
The 0.1µF capacitor on the bias line can be any good quality
capacitor (ceramic is recommended).
BIAS VOLTAGE
The bias voltage is an external voltage rail required to get
gate drive for the N-FET pass transistor. Bias voltage must
be in the range of 4.5 - 5.5V to assure proper operation of
the part.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the
regulator output from turning on if the bias voltage is below
approximately 4V.
SHUTDOWN OPERATION
Pulling down the shutdown (S/D) pin will turn-off the regula-
tor. Pin S/D must be actively terminated through a pull-up
resistor (10 kΩ to 100 kΩ) for a proper operation. If this pin
is driven from a source that actively pulls high and low (such
as a CMOS rail to rail comparator), the pull-up resistor is not
required. This pin must be tied to V_BIAS if not used.
POWER DISSIPATION/HEATSINKING
A heatsink may be required depending on the maximum
power dissipation and maximum ambient temperature of the
application. Under all possible conditions, the junction tem-
perature must be within the range specified under operating
conditions. The total power dissipation of the device is given
by:
P_D = (V_IN−V_OUT)I_OUT+ (V_IN)I_GND
where I_GND is the operating ground current of the device.
The maximum allowable temperature rise (T_Rmax) depends
on the maximum ambient temperature (T_Amax) of the appli-
cation, and the maximum allowable junction temperature
(T_Jmax):
T_Rmax = T_Jmax− T_Amax
The maximum allowable value for junction to ambient Ther-
mal Resistance, θ_JA, can be calculated using the formula:
θ_JA = T_Rmax / P_D
These parts are available in TO-220 and TO-263 packages.
The thermal resistance depends on amount of copper area
or heat sink, and on air flow. If the maximum allowable value
of θ_JA calculated above is ≥ 60 ˚C/W for TO-220 package
and ≥ 60 ˚C/W for TO-263 package no heatsink is needed
since the package can dissipate enough heat to satisfy these
requirements. If the value for allowable θ_JA falls below these
limits, a heat sink is required.
HEATSINKING TO-220 PACKAGE
The thermal resistance of a TO220 package can be reduced
by attaching it to a heat sink or a copper plane on a PC
board. If a copper plane is to be used, the values of θ_JA will
be same as shown in next section for TO263 package.
The heatsink to be used in the application should have a
heatsink to ambient thermal resistance,
θ_HA≤ θ_JA − θ_CH − θ_JC.
In this equation, θ_CH is the thermal resistance from the case
to the surface of the heat sink and θ_JC is the thermal resis-
tance from the junction to the surface of the case. θ_JC is
about 3˚C/W for a TO220 package. The value for θ_CH de-
pends on method of attachment, insulator, etc. θ_CH varies
between 1.5˚C/W to 2.5˚C/W. If the exact value is unknown,
2˚C/W can be assumed.
HEATSINKING TO-263 PACKAGE
The TO-263 package uses the copper plane on the PCB as
a heatsink. The tab of this package is soldered to the copper
plane for heat sinking. The graph below shows a curve for
the θ_JA of TO-263 package for different copper area sizes,
using a typical PCB with 1 ounce copper and no solder mask
over the copper area for heat sinking.
www.national.com
8