LMH6628 Datasheet, PDF (8/11 Pages) National Semiconductor (TI) – Dual Wideband, Low Noise, Voltage Feedback Op Amp

Typical Performance Characteristics (T_A = +25˚, A_V = +2, V_CC = ±5V, R_f =100Ω, R_L = 100Ω,
unless specified) (Continued)
Settling Time vs. Accuracy
20038548
Application Section
LOW NOISE DESIGN
Ultimate low noise performance from circuit designs using
the LMH6628 requires the proper selection of external resis-
tors. By selecting appropriate low valued resistors for R_F and
R_G, amplifier circuits using the LMH6628 can achieve output
noise that is approximately the equivalent voltage input
noise of 2nV/
multiplied by the desired gain (A_V).
DC BIAS CURRENTS AND OFFSET VOLTAGES
Cancellation of the output offset voltage due to input bias
currents is possible with the LMH6628. This is done by
making the resistance seen from the inverting and non-
inverting inputs equal. Once done, the residual output offset
voltage will be the input offset voltage (V_OS) multiplied by the
desired gain (A_V). National Application Note OA-7 offers
several solutions to further reduce the output offset.
OUTPUT AND SUPPLY CONSIDERATIONS
With ±5V supplies, the LMH6628 is capable of a typical
output swing of ±3.8V under a no-load condition. Additional
output swing is possible with slightly higher supply voltages.
For loads of less than 50Ω, the output swing will be limited by
the LMH6628’s output current capability, typically 85mA.
Output settling time when driving capacitive loads can be
improved by the use of a series output resistor. See the plot
labeled "R_S vs. C_L" in the Typical Performance section.
LAYOUT
Proper power supply bypassing is critical to insure good high
frequency performance and low noise. De-coupling capaci-
tors of 0.1µF should be placed as close as possible to the
power supply pins. The use of surface mounted capacitors is
recommended due to their low series inductance.
A good high frequency layout will keep power supply and
ground traces away from the inverting input and output pins.
Parasitic capacitance from these nodes to ground causes
frequency response peaking and possible circuit oscillation.
See OA-15 for more information. National suggests the
730036 (SOIC) dual op amp evaluation board as a guide for
high frequency layout and as an aid in device evaluation.
ANALOG DELAY CIRCUIT (ALL-PASS NETWORK)
The circuit in Figure 1 implements an all-pass network using
the LMH6628. A wide bandwidth buffer (LM7121) drives the
circuit and provides a high input impedance for the source.
As shown in Figure 2, the circuit provides a 13.1ns delay
(with R = 40.2Ω, C = 47pF). R_F and R_G should be of equal
and low value for parasitic insensitive operation.
FIGURE 1.
20038501
20038502
FIGURE 2. Delay Circuit Response to 0.5V Pulse
www.national.com
8