LMC1983 Datasheet, PDF (8/14 Pages) National Semiconductor (TI) – Digitally-Controlled Stereo Tone and Volume Circuit with Three Selectable Stereo Inputs

Application Information (Continued)
at lower output levels. If the load impedance is DC-coupled,
an increased quiescent current can flow. Latch-up may occur
if the total emitter current exceeds 5 mA. Thus, maximum
output voltage can be increased and much lower distortion
levels can be achieved using load impedances of at least
25 kΩ.
INPUT IMPEDANCE
The input impedance of pins 4, 5, 6, 23, 24 and 25 is defined
by internal bias resistors and is typically 50 kΩ.
The SELECT IN pins have an input impedance that varies
with the BASS and TREBLE control settings. The input im-
pedance is 100 kΩ at DC and 19 kΩ at 1 kHz when the con-
trols are set at 0 dB. Minimum input impedance of 30.4 kΩ at
DC and 16 kΩ at 1 kHz occurs when maximum boost is se-
lected. At 10 kHz the minimum input impedance, with the
tone controls flat, is 6.8 kΩ and, with the tone controls at
maximum boost, is 2.5 kΩ.
FIGURE 2. Input and Mode Select Circuitry
DS011279-4
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