ISP1504A1_07 Datasheet, PDF (8/81 Pages) NXP Semiconductors – ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver

NXP Semiconductors
ISP1504A1; ISP1504C1
ULPI HS USB OTG transceiver
7. Functional description
7.1 ULPI interface controller
The ISP1504x1 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface
(ULPI) Specification Rev. 1.1. This interface must be connected to the USB link.
The ULPI interface controller provides the following functions:
• ULPI-compliant interface and register set
• Allows full control over the USB peripheral, host and OTG functionality
• Parses the USB transmit and receive data
• Prioritizes the USB receive data, USB transmit data, interrupts and register operations
• Low-power mode
• Control of the V_BUS external power source
• V_BUS monitoring, charging and discharging
• 6-pin serial mode and 3-pin serial mode
• Generates RXCMDs; status updates
• Maskable interrupts
• Control over the ULPI bus state, allowing pins to 3-state or attach active weak
pull-down resistors
For more information on the ULPI protocol, see Section 9.
7.2 USB data serializer and deserializer
The USB data serializer prepares data to transmit on the USB bus. To transmit data, the
USB link sends a transmit command and data on the ULPI bus. The serializer performs
parallel-to-serial conversion, bit stuffing and NRZI encoding. For packets with a PID, the
serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end
of the packet. When the serializer is busy and cannot accept any more data, the ULPI
interface controller de-asserts NXT.
The USB data deserializer decodes data received from the USB bus. When data is
received, the deserializer strips the SYNC and EOP patterns, and then performs
serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data
payload. The ULPI interface controller sends data to the USB link by asserting DIR, and
then asserting NXT whenever a byte is ready. The deserializer also detects various
receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and
byte-alignment errors.
7.3 Hi-Speed USB (USB 2.0) ATX
The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to
transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for
USB peripheral, host and OTG implementations. The following circuitry is included:
• Differential drivers to transmit data at high-speed, full-speed and low-speed
ISP1504A1_ISP1504C1_1
Product data sheet
Rev. 01 — 6 August 2007
© NXP B.V. 2007. All rights reserved.
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