FPD87310 Datasheet, PDF (8/28 Pages) National Semiconductor (TI) – Universal Interface XGA Panel Timing Controller with RSDS™ (Reduced Swing Differential Signaling) and FPD-Link

AC Electrical Characteristics (Continued)
EEPROM INTERFACE TIMING
This table is provided for reference only.
Symbol
Parameter
f_SC
EE_SC Clock Frequency
SC:LOW Clock Low Period
SC:HIGH Clock High Period
SCD:TR EE_SC and EE_SD Rise Time
SCD:TF EE_SC and EE_SD Fall Time
HD:STA Start Condition Hold Time
HD:STO Stop Condition Hold Time
DL:DAT_H
DL:DAT_L
SU:DAT
Clock Falling Edge to Data High
Clock Falling Edge to Data Low
Data Latch Setup Time
HD:DAT Data Latch Hold Time
BUF
Bus Free Time
Conditions
R_P = 4.7 kΩ, C_L = 50 pF
R_P = 4.7 kΩ, C_L = 50 pF
R_P = 4.7 kΩ, C_L = 50 pF
R_P = 4.7 kΩ, C_L = 50 pF
R_P = 4.7 kΩ, C_L = 50 pF
R_P = 4.7 kΩ, C_L = 50 pF
R_P = 4.7 kΩ, C_L = 50 pF
R_P = 4.7 kΩ, C_L = 50 pF
R_P = 4.7 kΩ, C_L = 50 pF
R_P = 4.7 kΩ, C_L = 50 pF
R_P = 4.7 kΩ, C_L = 50 pF
Min
Typ
Max
Units
100
kHz
4.7
µs
4.0
µs
1.0
µs
0.3
µs
4.0
µs
0.6
µs
400
ns
400
ns
250
ns
5
µs
4.7
µs
FIGURE 9. EEPROM Interface Bus Timing
DS101077-14
FIGURE 10. EEPROM Sequential Read
DS101077-15
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