DP83916 Datasheet, PDF (76/96 Pages) National Semiconductor (TI) – SONICTM-16 Systems-Oriented Network Interface Controller

7 0 AC and DC Specifications (Continued)
MEMORY WRITE BMODE e 0 ASYNCHRONOUS MODE
TL F 11722 – 63
Number
Parameter
20 MHz
Min
Max
Units
T9
BSCK to Address Valid
34
ns
T10
Address Hold Time from BSCK
5
ns
T11b
BSCK to ADS DS ECS Low
30
ns
T12b
BSCK to ADS ECS High
32
ns
T13
BSCK to DS High
36
ns
T15
ADS High Width (Note 2)
bcyc b 5
ns
T18
Write Data Strobe Low Width (Notes 2 4)
bcyc b 5
ns
T32a
Ready Asynch Setup to BSCK (Note 3)
8
ns
T33a
Ready Asynch Hold from BSCK
5
ns
T36
BSCK to Memory Write Data Valid
70
ns
T37
BSCK to MWR (Write) Valid (Note 1)
30
ns
T39
Write Data Valid to
bcyc b 40
ns
Data Strobe Low (Note 2)
T40
Write Data Hold Time from BSCK
10
ns
Note 1 For successive read operations MWR remains low and for successive write operations MWR remains high During RBA and TBA transfers the MWR
signal will stay either high or low for the entire burst of the transfer During RDA and TDA transfers the MWR signal will switch on the rising edge of a Ti (idle) state
that is inserted between the read and the write operation
Note 2 bcyc e bus clock cycle time (T3)
Note 3 This setup time assures that the SONIC-16 terminates the memory cycle on the next bus clock (BSCK) RDYi does not need to be synchronized to the bus
clock though since it is an asynchronous input in this case RDYi is sampled during the falling edge of BSCK If the SONIC-16 samples RDYi low during the T1
cycle the SONIC-16 will finish the current access in a total of two bus clocks instead of three which would be the case if RDYi had been sampled low during
T2(wait) (This is assuming that programmable wait states are set to 0)
Note 4 DS will only be asserted if the bus cycle has at least one wait state inserted
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