LMX2306_04 Datasheet, PDF (7/19 Pages) National Semiconductor (TI) – PLLatinum™ Low Power Frequency Synthesizer for RF Personal Communications

1.0 Functional Description
The simplified block diagram below shows the 21-bit data register, a 14-bit R Counter, an 18-bit N Counter, and a 18-bit Function
Latch (intermediate latches are not shown). The data stream is shifted (on the rising edge of LE) into the DATA input, MSB first.
The last two bits are the Control Bits. The DATA is transferred into the counters as follows:
Control
C1
C2
0
0
1
0
0
1
1
1
DATA Location
R Counter
N Counter
Function Latch
Initialization
10012704
1.1 PROGRAMMABLEREFERENCE DIVIDER
If the Control Bits are [C₁, C₂] = [0,0], data is transferred from the 21-bit shift register into a latch that sets the 14-bit R Counter.
The 4 bits R15–R18 are for test modes, and should be set to 0 for normal use. The LD precision bit, R19, is described in the
LOCK DETECT OUTPUT CHARACTERISTICS section. Serial data format is shown below.
Note: R15 to R18 are test modes and should be zero for normal operation.
Data is shifted in MSB first.
10012705
1.1.1 14-bit Programmable Reference Divider Ratio (R Counter)
Divide
R
R
R
R
R
RRRRRRRRR
Ratio
14
13
12
11
10
9
8
7
6
5
4
3
2
1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes: Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 16383
R1 to R14: These bits select the divide ratio of the programmable reference divider.
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