DS90LV019 Datasheet, PDF (7/10 Pages) National Semiconductor (TI) – 3.3V or 5V LVDS Driver/Receiver

Test Circuits and Timing Waveforms (Continued)
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FIGURE 9. Receiver TRI-STATE Delay Waveforms TRI-STATE Delay Waveforms
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FIGURE 10. Terminated Input Fail-Safe Circuit
Typical Application Diagram
Applications Information
The DS90LV019 has two control pins, which allows the de-
vice to operate as a driver, a receiver or both driver and a re-
ceiver at the same time. There are a few common practices
which should be implied when designing PCB for LVDS sig-
naling. Recommended practices are:
• Use at least 4 PCB board layer (LVDS signals, ground,
power and TTL signals).
• Keep drivers and receivers as close to the (LVDS port
side) connector as possible.
• Bypass each LVDS device and also use distributed bulk
capacitance. Surface mount capacitors placed close to
power and ground pins work best. Two or three multi-
layer ceramic (MLC) surface mount capacitors 0.1 µF,
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and 0.01 µF in parallel should be used between each V_CC
and ground. The capacitors should be as close as pos-
sible to the V_CC pin.
• Use controlled impedance traces which match the differ-
ential impedance of your transmission medium (i.e.,
Cable) and termination resistor.
• Use the termination resistor which best matches the dif-
ferential impedance of your transmission line.
• Isolate TTL signals from LVDS signals.
MEDIA (CABLE AND CONNECTOR) SELECTION:
• Use controlled impedance media. The cables and con-
nectors should have a matched differential impedance of
about 100Ω.
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