ADC12DL065 Datasheet, PDF (7/26 Pages) National Semiconductor (TI) – Dual 12-Bit, 65 MSPS, 3.3V, 360mW A/D Converter

DC and Logic Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A = V_D = +3.3V, V_DR =
+2.5V, PD = 0V, External V_REF = +1.0V, f_CLK = 65 MHz, f_IN = 10 MHz, t_r = t_f = 2 ns, C_L = 15 pF/pin, Duty Cycle Stabilizer On,
parallel output mode. Boldface limits apply for T_J = T_MIN to T_MAX: all other limits T_J = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical Limits
(Note 10) (Note 10)
Units
(Limits)
V_OUT(1)
V_OUT(0)
I_OZ
+I_SC
Logical “1” Output Voltage
Logical “0” Output Voltage
TRI-STATE^® Output Current
Output Short Circuit Source
Current
I_OUT = −0.5 mA
V_DR = 2.5V
V_DR = 3V
2.3
V (min)
2.7
V (min)
I_OUT = 1.6 mA, V_DR = 3V
0.4
V (max)
V_OUT = 2.5V or 3.3V
100
nA
V_OUT = 0V
−100
nA
V_OUT = 0V
−20
mA
−I_SC
Output Short Circuit Sink Current
C_OUT
Digital Output Capacitance
POWER SUPPLY CHARACTERISTICS
V_OUT = V_DR
20
mA
5
pF
I_A
Analog Supply Current
I_D
Digital Supply Current
I_DR
Digital Output Supply Current
Total Power Consumption
PSRR1 Power Supply Rejection Ratio
PD Pin = DGND, V_REF = V_A
90
PD Pin = V_D
12
PD Pin = DGND
19
PD Pin = V_D , f_CLK = 0
0
PD Pin = DGND, C_L = 10 pF (Note 14)
15
PD Pin = V_D, f_CLK = 0
0
PD Pin = DGND, C_L = 10 pF (Note 15)
360
PD Pin = V_D
36
Rejection of Full-Scale Error with
62
V_A =3.0V vs. 3.6V
108
mA (max)
mA
22
mA (max)
mA
mA
mA
430
mW (max)
mW
dB
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A = V_D = +3.3V, V_DR =
+2.5V, PD = 0V, External V_REF = +1.0V, f_CLK = 65 MHz, f_IN = 10 MHz, t_r = t_f = 2 ns, C_L = 15 pF/pin, Duty Cycle Stabilizer On,
parallel output mode. Boldface limits apply for T_J = T_MIN to T_MAX: all other limits T_J = 25˚C (Notes 7, 8, 9, 12)
Symbol
Parameter
Conditions
Typical Limits
(Note 10) (Note 10)
Units
(Limits)
f_CLK1
f_CLK2
t_CH
t_CL
t_r, t_f
t_CH
t_CL
t_r, t_f
t_CONV
Maximum Clock Frequency
Minimum Clock Frequency
Clock High Time
Clock Low Time
Clock Rise and Fall Times
Clock High Time
Clock Low Time
Clock Rise and Fall Times
Conversion Latency
Duty Cycle Stabilizer On
Duty Cycle Stabilizer On
Duty Cycle Stabilizer On
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer Off
Parallel mode
65
MHz (min)
15
MHz
7.7
3
ns (min)
7.7
3
ns (min)
2
4
ns (max)
7.7
6.2
ns (min)
7.7
6.2
ns (min)
2
ns (max)
Clock
7
Cycles
Data Output Delay after Rising
t_OD
Clock Edge
Parallel mode
3.5
ns (min)
6.0
9
ns (max)
t_CONV
Conversion Latency
Multiplex mode, Channel A
Clock
7.5
Cycles
t_CONV
Conversion Latency
Multiplex mode, Channel B
Clock
8
Cycles
Data Output Delay after Clock
t_OD
Edge
Multiplex mode
3.5
ns (min)
6.0
8
ns (max)
t_SKEW
t_AD
ABb to Data Skew
Aperture Delay
±0.5
2
ns (max)
ns
7
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