DP83820 Datasheet, PDF (67/87 Pages) National Semiconductor (TI) – 10/100/1000 Mb/s PCI Ethernet Network Interface Controller

4.0 Register Set (Continued)
4.2.33 Receive Descriptor Pointer 3 Register
This register points to the Receive Descriptor for Priority Queue 3 (highest priority).
Tag: RXDP3
Size: 32 bits
Hard Reset: 00000000h
Offset: 00B8h
Access: Read Write
Soft Reset: 00000000h
bit
31-3
2-0
tag
RXDP3
description
usage
Receive
The current value of the receive descriptor pointer for Priority Queue 3. Packets will be
Descriptor Pointer stored in Priority Queue 3 based on the number of priority queues enabled and the
3
priority field in the VLAN tag. When the receive state machine is idle, software must set
RXDP3 to the address of an available receive descriptor, and then enable the queue by
writing to the RXE bit in the CR with the RXPRI[3] bit set. While the receive state machine
is active, RXDP3 will follow the state machine as it advances through a linked list of
available descriptors. If the link field of the current receive descriptor is NULL (signifying
the end of the list), RXDP3 will not advance, but will remain on the current descriptor. Any
subsequent writes to the RXE bit of the CR register will cause the receive state machine
to reread the link field of the current descriptor to check for new descriptors that may have
been appended to the end of the list. Software should not write to this register unless the
receive state machine is idle. Receive descriptors must be aligned on 64-bit boundaries
(A2-A0 must be zero).
unused
4.2.34 VLAN/IP Receive Control Register
This register allows enabling of the various VLAN tag handling features and IP Checksum offload features.
Tag: VRCR
Size: 32 bits
Hard Reset: 00000000h
Offset: 00BCh
Access: Read Write
Soft Reset: 00000000h
bit
31-8
7
6
5
4
3
2
1
0
tag
RUDPE
RTCPE
RIPE
IPEN
DUTF
DVTF
VTREN
VTDEN
description
usage
unused
Reject UDP
When set to 1, all packets with UDP headers that have errors in the UDP checksum field
Checksum Errors will be rejected. If IPEN is 0, this bit will be ignored.
Reject TCP
When set to 1, all packets with TCP headers that have errors in the TCP checksum field
Checksum Errors will be rejected. If IPEN is 0, this bit will be ignored.
Reject IP
When set to 1, all packets with IP headers that have errors in the IP checksum field will be
Checksum Errors rejected. If IPEN is 0, this bit will be ignored.
IP Checksum
Enable
When set to a 1, the receiver will detect IP, TCP, and UDP headers, and validate the
checksum fields.
Discard Untagged Receiver will discard any frames without a1 VLAN tag.
Frames
Discard VLAN Receiver will discard any frames with a VLAN tag.
Tagged Frames
VLAN Tag
Enables stripping of the VLAN tag upon detection. If VTDEN is not set, then this bit will
Removal Enable have no effect.
VLAN Tag
Enable detection of VLAN packets based on VLAN type field as configured in the VLAN
Detection Enable Data Register. VLAN status, including user_priority, CFI and VID fields, will be posted in
the EXTSTS field of the receive packet descriptor.
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