SC14422 Datasheet, PDF (6/7 Pages) National Semiconductor (TI) – Complete Baseband Processor for DECT Base Stations

Table 1: Pin Description)
PIN NAME
RSTn
HOLDn
or MI
NR
TYPE
68
1
69
2
ACSn
70
5
AD3..0
DAB7..0
RCSn
71-74
1
82-75
1
83
5
AD10
84
1
RDn
85
1
AD11
86
1
AD9
87
1
AD8
88
1
AD13
89
1
AD14
90
1
AD17
91
1
WRn
92
1
AD16,15, 12 93-95
1
AD7-4
96-99
1
CLK1M
100
1
DESCRIPTION
INPUT. Active low Reset.
INPUT/OUTPUT with fixed pull up. Selects HOLD mode. If set to ‘0’, the CR16A
processor will terminate its current instruction and the ADx, WRN, RDN will go TRI-
STATE. In this mode an external CR16A can control the SC14422 completely.
In Emulation mode MI output is automatically selected. Then this pin goes high if
an internal interrupt is asserted. In core mode this pin is a maskable interrupt input
MI to the CR16A core.
OUTPUT. Auxiliary Chip Select not. This signal becomes low if the address range
is within the programmed address range.
OUTPUT. Address bit 3 to 0. In HOLD mode these pins are input.
INPUT/OUTPUT. Data bus bit 7..0
OUTPUT. ROM Chip Select not. Low active if none of the internal peripherals or the
ACSn is addressed.
OUTPUT. Address bit 10. In HOLD mode this pin is input.
OUTPUT. Active low read. In HOLD mode this pin is input.
OUTPUT. Address bit 11. In HOLD mode this pin is input.
OUTPUT. Address bit 9. In HOLD mode this pin is input.
OUTPUT. Address bit 8. In HOLD mode this pin is input.
OUTPUT. Address bit 13. In HOLD mode this pin is input.
OUTPUT. Address bit 14. In HOLD mode this pin is input.
OUTPUT. Address bit 17. In HOLD mode this pin is output.
OUTPUT. Active low write signal. In HOLD mode this pin is input.
OUTPUT. Address bit 16,15 & 12. In HOLD mode these pins are input.
OUTPUT. Address bit 7 to 4. In HOLD mode these pins are input.
OUTPUT. Fixed bit clock output (1.152Mhz). Synchronized to the DECT bit clock.
Will be logic ‘0’ if the DECT Dedicated Instruction Processor (DIP) is frozen.
Will be logic ‘1’ after a hardware reset (RSTN) or software reset (DEBUG_REG[1]).
NOTE: All digital outputs can sink/source 2 mA unless otherwise specified. All digital inputs are Schmitt trigger
types. After reset all I/Os are set to input and all pull-up or pull-down resistors are enabled. The p0[0] pull-
up resistor is disabled at start-up.
Copyright 1998 National Semiconductor Corp.
6
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