LP38841-ADJ Datasheet, PDF (6/10 Pages) National Semiconductor (TI) – 0.8A Ultra Low Dropout Adjustable Linear Regulators Stable with Ceramic Output Capacitors

Load Transient Response
Load Transient Response
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Application Hints
SETTING THE OUTPUT VOLTAGE
(Refer to Typical Application Circuit)
The output voltage is set using the resistive divider R1 and
R2. The output voltage is given by the formula:
V_OUT = V_ADJ x (1 + R1 / R2)
The value of R2 must be 10k or less for proper operation.
EXTERNAL CAPACITORS
To assure regulator stability, input and output capacitors are
required as shown in the Typical Application Circuit.
OUTPUT CAPACITOR
An output capacitor is required on the LP3884X devices for
loop stability. The minimum value of capacitance necessary
depends on type of capacitor: if a solid Tantalum capacitor is
used, the part is stable with capacitor values as low as 4.7µF.
If a ceramic capacitor is used, a minimum of 22 µF of capac-
itance must be used (capacitance may be increased without
limit). The reason a larger ceramic capacitor is required is that
the output capacitor sets a pole which limits the loop band-
width. The Tantalum capacitor has a higher ESR than the
ceramic which provides more phase margin to the loop, there-
by allowing the use of a smaller output capacitor because
adequate phase margin can be maintained out to a higher
crossover frequency. The tantalum capacitor will typically al-
so provide faster settling time on the output after a fast chang-
ing load transient occurs, but the ceramic capacitor is superior
for bypassing high frequency noise.
The output capacitor must be located less than one centime-
ter from the output pin and returned to a clean analog ground.
Care must be taken in choosing the output capacitor to ensure
that sufficient capacitance is provided over the full operating
temperature range. If ceramics are selected, only X7R or X5R
types may be used because Z5U and Y5F types suffer severe
loss of capacitance with temperature and applied voltage and
may only provide 20% of their rated capacitance in operation.
INPUT CAPACITOR
The input capacitor is also critical to loop stability because it
provides a low source impedance for the regulator. The min-
imum required input capacitance is 10 µF ceramic (Tantalum
not recommended). The value of C_IN may be increased with-
out limit. As stated above, X5R or X7R must be used to ensure
sufficient capacitance is provided. The input capacitor must
be located less than one centimeter from the input pin and
returned to a clean analog ground.
FEED FORWARD CAPACITOR
(Refer to Typical Application Circuit)
A capacitor placed across R1 can provide some additional
phase margin and improve transient response. The capacitor
C_FF and R1 form a zero in the loop response given by the
formula:
F_Z = 1 / (2 x π x C_FF x R1)
For best effect, select C_FF so the zero frequency is approxi-
mately 70 kHz. The phase lead provided by C_FF drops as the
output voltage gets closer to 0.56V (and R1 reduces in value).
The reason is that C_FF also forms a pole whose frequency is
given by:
F_P = 1 / (2 x π x C_FF x R1 // R2)
As R1 reduces, the two equations come closer to being equal
and the pole and zero begin to cancel each other out which
removes the beneficial phase lead of the zero.
BIAS CAPACITOR
The 0.1µF capacitor on the bias line can be any good quality
capacitor (ceramic is recommended).
BIAS VOLTAGE
The bias voltage is an external voltage rail required to get gate
drive for the N-FET pass transistor. Bias voltage must be in
the range of 4.5 - 5.5V to assure proper operation of the part.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the
regulator output from turning on if the bias voltage is below
approximately 3.8V.
SHUTDOWN OPERATION
Pulling down the shutdown (S/D) pin will turn-off the regulator.
The S/D pin must be actively terminated through a pull-up re-
sistor (10 kΩ to 100 kΩ) for a proper operation. If this pin is
driven from a source that actively pulls high and low (such as
a CMOS rail to rail comparator), the pull-up resistor is not re-
quired. This pin must be tied to Vin if not used.
POWER DISSIPATION/HEATSINKING
Heatsinking for the PSOP-8 package is accomplished by al-
lowing heat to flow through the exposed DAP on the bottom
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