LMH0307 Datasheet, PDF (6/14 Pages) National Semiconductor (TI) – 3 Gbps HD/SD SDI Dual Cable Driver with Cable Detect

Device Operation
INPUT INTERFACING
The LMH0307 accepts either differential or single-ended in-
put. For single-ended operation, the unused input must be
properly terminated.
OUTPUT INTERFACING
The LMH0307 uses current mode outputs. Single-ended out-
put levels are 800 mV_P-P into 75Ω AC-coupled coaxial cable
with an R_REF resistor of 750Ω. The R_REF resistor is connected
between the R_REF pin and V_CC. The only resistor value that
should be used for R_REF is 750Ω.
The R_REF resistor should be placed as close as possible to
the R_REF pin. In addition, the copper in the plane layers below
the R_REF network should be removed to minimize parasitic
capacitance.
OUTPUT SLEW RATE CONTROL
The LMH0307 output rise and fall times are selectable for ei-
ther SMPTE 259M or SMPTE 424M / 292M compliance via
the SD/HD pin. For slower rise and fall times, or SMPTE 259M
compliance, SD/HD is set high. For faster rise and fall times,
or SMPTE 424M and SMPTE 292M compliance, SD/HD is
set low. SD/HD may also be controlled using the SMBus, pro-
vided the SD/HD pin is held low.
OUTPUT ENABLE
The SDO0/SDO0 and SDO1/SDO1output drivers can be en-
abled or disabled with the ENABLE pin. When set low, both
output drivers are powered off and the LMH0307 enters a
deep power save mode. ENABLE has an internal pullup.
INPUT LOSS OF SIGNAL DETECTION (LOS)
The LMH0307 detects when the input signal does not have a
video-like pattern. Self oscillation and low levels of noise are
rejected. This loss of signal detect allows a very sensitive in-
put stage that is robust against coupled noise without any
degradation of jitter performance.
Via the SMBus, the loss of signal detect can either add an
input offset or mute the outputs. An offset is added by default.
Additionally, the loss of signal detect can be linked to the EN-
ABLE functionality so that when the LOS goes low, ENABLE
will also go low.
OUTPUT CABLE DETECTION
The LMH0307 detects when an output is locally terminated.
When a video signal (or AC test signal) is present on SDI, the
device senses the SDO and SDO amplitudes. If the output is
not properly terminated (via a terminated cable or local ter-
mination), the amplitude will be higher than expected, and the
Termination Fault signal is asserted. The Termination Fault
signal is de-asserted when the proper termination is applied.
This feature allows the system designer the flexibility to react
to cable attachment and removal. Note that a long length of
cable will look like a proper termination at the device output.
Also note that the cable driver must be enabled for the termi-
nation detection to operate.
SMBus Interface
The System Management Bus (SMBus) is a two-wire inter-
face designed for the communication between various sys-
tem component chips. By accessing the control functions of
the circuit via the SMBus, pincount is kept to a minimum while
allowing a maximum amount of versatility. The LMH0307 has
several internal configuration registers which may be ac-
cessed via the SMBus.
The 7-bit default address for the LMH0307 is 17h. The LSB
is set to 0b for a WRITE and 1b for a READ, so the 8-bit default
address for a WRITE is 2Eh and the 8-bit default address for
a READ is 2Fh. The SMBus address may be dynamically
changed.
In applications where there might be several LMH0307s, the
SDA, SCL, and FAULT pins can be shared. The SCL, SDA,
and FAULT pins are open drain and require external pullup
resistors. Multiple LMH0307s may have the FAULT pin wire
ORed. This signal becomes active when either loss of signal
is detected or any termination faults are detected. The regis-
ters may be read in order to determine the cause. Additionally,
each signal can be masked from the FAULT pin.
TRANSFER OF DATA VIA THE SMBus
During normal operation the data on SDA must be stable dur-
ing the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High
indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High
indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding
t_BUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for t_HIGH then
the bus will transfer to the IDLE state.
SMBus TRANSACTIONS
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
READING A REGISTER
To read a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the
READ transfer.
10. The Host drives a STOP condition.
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