LMC555_06 Datasheet, PDF (6/12 Pages) National Semiconductor (TI) – CMOS Timer

Application Information (Continued)
FREQUENCY DIVIDER
The monostable circuit of Figure 1 can be used as a fre-
quency divider by adjusting the length of the timing cycle.
Figure 7 shows the waveforms generated in a divide by three
circuit.
V_CC = 5V
TIME = 20 µs/Div.
R_A = 3.9 kΩ
R_B = 9 kΩ
C = 0.01 µF
Top Trace: Output 5 V/Div.
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Bottom Trace: Capacitor Voltage 1 V/Div.
FIGURE 5. Astable Waveforms
The charge time (output high) is given by
t₁ = 0.693 (R_A + R_B)C
And the discharge time (output low) by:
t₂ = 0.693 (R_B)C
Thus the total period is:
T = t₁ + t₂ = 0.693 (R_A + R_B)C
The frequency of oscillation is:
V_CC = 5V
Top Trace: Input 4 V/Div.
TIME = 20 µs/Div. Middle Trace: Output 2 V/Div.
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R_A = 9.1 kΩ
C = 0.01 µF
Bottom Trace: Capacitor 2 V/Div.
FIGURE 7. Frequency Divider Waveforms
PULSE WIDTH MODULATOR
When the timer is connected in the monostable mode and
triggered with a continuous pulse train, the output pulse
width can be modulated by a signal applied to the Control
Voltage Terminal. Figure 8 shows the circuit, and in Figure 9
are some waveform examples.
Figure 6 may be used for quick determination of these RC
Values. The duty cycle, as a fraction of total period that the
output is low, is:
FIGURE 8. Pulse Width Modulator
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FIGURE 6. Free Running Frequency
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