DS90LV110T Datasheet, PDF (6/9 Pages) National Semiconductor (TI) – 1 to 10 LVDS Data/Clock Distributor

DS90LV110 Pin Descriptions
Pin Name
IN+
IN -
OUT+
OUT -
EN
# of Pin
1
1
10
10
1
Input/Output
I
I
O
O
I
V_SS
3
P
V_DD
2
P
Description
Non-inverting LVDS input
Inverting LVDS input
Non-inverting LVDS Output
Inverting LVDS Output
This pin has an internal pull-down when left open. A
logic low on the Enable puts all the LVDS outputs into
TRI-STATE and reduces the supply current.
Ground (all ground pins must be tied to the same
supply)
Power Supply (all power pins must be tied to the same
supply)
Application Information
Input fail-safe:
The receiver inputs of the DS90LV110 do not have internal
fail-safe biasing. For point-to-point and multi-drop applica-
tions with a single source, fail-safe biasing may not be
required. When the driver is off, the link is in-active. If
fail-safe biasing is required, this can be accomplished with
external high value resistors. The IN+ should be pull to Vcc
with 10kΩ and the IN− should be pull to Gnd with 10kΩ. This
provides a slight positive differential bias, and sets a known
HIGH state on the link with a minimum amount of distortion.
See AN-1194 for additional informations.
LVDS Inputs termination:
The LVDS Receiver input must have a 100Ω termination
resistor placed as close as possible across the input pins.
Unused Control Inputs:
The EN control input pin has internal pull down device. If left
open, the 10 outputs will default to TRI-STATE.
Expanding the Number of Output Ports:
To expand the number of output ports, more than one
DS90LV110 can be used. Total propagation delay through
the devices should be considered to determine the maxi-
mum expansion. Adding more devices will increase the out-
put jitter due to each pass.
PCB Layout and Power System Bypass:
Circuit board layout and stack-up for the DS90LV110 should
be designed to provide noise-free power to the device. Good
layout practice also will separate high frequency or high level
inputs and outputs to minimize unwanted stray noise pickup,
feedback and interference. Power system performance may
be greatly improved by using thin dielectrics (4 to 10 mils) for
power/ground sandwiches. This increases the intrinsic ca-
pacitance of the PCB power system which improves power
supply filtering, especially at high frequencies, and makes
the value and placement of external bypass capacitors less
critical. External bypass capacitors should include both RF
ceramic and tantalum electrolytic types. RF capacitors may
use values in the range 0.01 µF to 0.1 µF. Tantalum capaci-
tors may be in the range 2.2 µF to 10 µF. Voltage rating for
tantalum capacitors should be at least 5X the power supply
voltage being used. It is recommended practice to use two
vias at each power pin of the DS90LV110 as well as all RF
bypass capacitor terminals. Dual vias reduce the intercon-
nect inductance by up to half, thereby reducing interconnect
inductance and extending the effective frequency range of
the bypass components.
The outer layers of the PCB may be flooded with additional
ground plane. These planes will improve shielding and iso-
lation as well as increase the intrinsic capacitance of the
power supply plane system. Naturally, to be effective, these
planes must be tied to the ground supply plane at frequent
intervals with vias. Frequent via placement also improves
signal integrity on signal transmission lines by providing
short paths for image currents which reduces signal distor-
tion. The planes should be pulled back from all transmission
lines and component mounting pads a distance equal to the
width of the widest transmission line or the thickness of the
dielectric separating the transmission line from the internal
power or ground plane(s) whichever is greater. Doing so
minimizes effects on transmission line impedances and re-
duces unwanted parasitic capacitances at component
mounting pads.
There are more common practices which should be followed
when designing PCBs for LVDS signaling. Please see Appli-
cation Note: AN-1108 for additional information.
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