DS90LV001_08 Datasheet, PDF (6/16 Pages) National Semiconductor (TI) – 800 Mbps LVDS Buffer

DS90LV001 Pin Descriptions (SOIC and LLP)
Pin Name
GND
IN −
IN+
NC
V_CC
OUT+
OUT -
EN
DAP
Pin #
1
2
3
4
5
6
7
8
NA
Input/Output
P
I
I
P
O
O
I
NA
Description
Ground
Inverting receiver LVDS input pin
Non-inverting receiver LVDS input pin
No Connect
Power Supply, 3.3V ± 0.3V.
Non-inverting driver LVDS output pin
Inverting driver LVDS output pin
Enable pin. When EN is LOW, the driver is disabled and the LVDS
outputs are in TRI-STATE. When EN is HIGH, the driver is enabled.
LVCMOS/LVTTL levels.
Die Attach Pad or DAP (LLP Package only). The DAP is NOT connected
to the device GND nor any other pin. It is still recommended to connect
the DAP to a GND plane of a PCB for enhenced heat dissipation.
Typical Applications
Backplane Stub-Hider Application
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