DS90LT012A_08 Datasheet, PDF (6/8 Pages) National Semiconductor (TI) – 3V LVDS Single CMOS Differential Line Receiver

(a stable known state of HIGH output voltage) for floating,
terminated or shorted receiver inputs.
1. Open Input Pins. The DS90LV012A and DS90LT012A
are single receiver devices. It is not required to tie the
receiver inputs to ground or any supply voltage. Internal
failsafe circuitry will guarantee a HIGH, stable output
state for open inputs.
2. Terminated Input. If the driver is disconnected (cable
unplugged), or if the driver is in a power-off condition, the
receiver output will again be in a HIGH state, even with
the end of cable 100Ω termination resistor across the
input pins. The unplugged cable can become a floating
antenna which can pick up noise. If the cable picks up
more than 10mV of differential noise, the receiver may
see the noise as a valid signal and switch. To insure that
any noise is seen as common-mode and not differential,
a balanced interconnect should be used. Twisted pair
cable will offer better balance than flat ribbon cable.
3. Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output will remain
in a HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (GND to
2.4V). It is only supported with inputs shorted and no
external common-mode voltage applied.
External lower value pull up and pull down resistors (for a
stronger bias) may be used to boost fail-safe in the presence
of higher noise levels. The pull up and pull down resistors
should be in the 5kΩ to 15kΩ range to minimize loading and
waveform distortion to the driver. The common-mode bias
point should be set to approximately 1.2V (less than 1.75V)
to be compatible with the internal circuitry.
Pin Descriptions
The DS90LV012A and DS90LT012A are compliant to the
original ANSI EIA/TIA-644 specification and is also compliant
to the new ANSI EIA/TIA-644-A specification with the excep-
tion the newly added ΔI_IN specification. Due to the internal fail-
safe circuitry, ΔI_IN cannot meet the 6µA maximum specified.
This exception will not be relevant unless more than 10 re-
ceivers are used.
Additional information on fail-safe biasing of LVDS devices
may be found in AN-1194.
PROBING LVDS TRANSMISSION LINES
Always use high impedance (> 100kΩ), low capacitance
(< 2 pF) scope probes with a wide bandwidth (1 GHz) scope.
Improper probing will give deceiving results.
CABLES AND CONNECTORS, GENERAL COMMENTS
When choosing cable and connectors for LVDS it is important
to remember:
Use controlled impedance media. The cables and connectors
you use should have a matched differential impedance of
about 100Ω. They should not introduce major impedance dis-
continuities.
Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax) for noise re-
duction and signal quality. Balanced cables tend to generate
less EMI due to field canceling effects and also tend to pick
up electromagnetic radiation a common-mode (not differential
mode) noise which is rejected by the receiver.
For cable distances < 0.5M, most cables can be made to work
effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category
3) twisted pair cable works well, is readily available and rela-
tively inexpensive.
Package Pin Number
SOT23
LLP
4
1
3
3
5
8
1
6
2
2, 7
4, 5
Pin Name
Description
IN−
IN+
TTL OUT
V_DD
GND
NC
Inverting receiver input pin
Non-inverting receiver input pin
Receiver output pin
Power supply pin, +3.3V ± 0.3V
Ground pin
No connect
Ordering Information
Operating
Temperature
−40°C to +85°C
Package Type/
Number
MF05A
LDA08A
Order Numbers
DS90LV012ATMF, DS90LT012ATMF
DS90LV012ATLD, DS90LT012ATLD
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