DS90CF384A Datasheet, PDF (6/16 Pages) National Semiconductor (TI) – +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65 MHz

AC Timing Diagrams (Continued)
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FIGURE 6. DS90CF384A/DS90CF364A (Receiver) Clock In to Clock Out Delay
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FIGURE 7. DS90CF384A/DS90CF364A (Receiver) Phase Lock Loop Set Time
FIGURE 8. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF384A
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