DS8908B Datasheet, PDF(6/10 Page) National Semiconductor (TI) – AM/FM Digital Phase-Locked Loop Frequency Synthesizer

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DS8908B Datasheet, PDF (6/10 Pages) National Semiconductor (TI) – AM/FM Digital Phase-Locked Loop Frequency Synthesizer

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Timing Diagrams (Continued)

AM FM Frequency Synthesizer (Scan Mode)

Timing diagrams are not drawn to scale Scale within any one drawing may not be consistent and intervals are defined positive as drawn

TL F 5111 12

SERIAL DATA ENTRY INTO THE DS8908B

Serial information entry into the DS8908B is enabled by a

low level on the ENABLE input One binary bit is then ac-

cepted from the DATA input with each positive transition of

the CLOCK input The CLOCK input must be low for the

specified time preceding and following the negative tran-

sition of the ENABLE input

The first two bits accepted following the negative transition

of the ENABLE input are interpreted as address If these

address bits are not 1 1 no further information will be ac-

cepted fromt he DATA inputs and the internal data latches

will not be changed when ENABLE returns high

If these first two bits are 1 1 then all succeeding bits are

accepted as data and are shifted successively into the in-

ternal shift register as long as ENABLE remains low

Any data bits preceding the 19th to last bit will be shifted

out and thus are irrelevant Data bits are counted as any

bits following two valid address bits (1 1) with the ENABLE

low When the ENABLE input returns high any further serial

data entry is inhibited Upon this positive transition the data

in the internal shift register is transferred into the internal

data latches Note that until this time the states of the inter-

nal data latches have remained unchanged

These data bits are interpreted as follows

Data Bit Position

Data Interpretation

Last

Bit 19 Output (Pin 2)

2nd to Last

Bit 18 Output (Pin 1)

3rd to Last

Ref Freq Select Bit(1)17

4th to Last

Ref Freq Select Bit(1)16

5th to Last

6th to Last

AM FM Select Bit 15

(213)

7th to Last

(212)

8th to Last

9th to Last

10th to Last

(211)

(210)

(29)

11th to Last

(28)

12th to Last

13th to Last

14th to Last

(27)

(26)

dN(2)

(25)

15th to Last

(24)

16th to Last

17th to Last

18th to Last

19th to Last

(23)

-(22)

(21)

LSB of dN(20)

Note 1 See Reference Frequency Select Truth Table

Note 2 The actual divide code is Na1 ie the number loaded plus 1

Truth Table

Reference Frequency Selection Truth Table

Serial Data

Bit 16

Bit 17

Reference

Frequency

(kHz)

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