DS32EL0124_09 Datasheet, PDF (6/28 Pages) National Semiconductor (TI) – 125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface

LVCMOS Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. Applies to LT_EN, GPIO0, GPIO1,
GPIO2, RX_MUX_SEL, DC_B, RESET, RS, LOCK. (Note 2, Note 4, Note 5)
Symbol
Parameter
Conditions
Min Typ Max Units
V_IH
High Level Input Voltage
V_IL
Low Level Input Voltage
V_OH
High Level Output Voltage
V_OL
Low Level Output Voltage
V_CL
Input Clamp Voltage
I_IN
Input Current
I_OS
Output Short Circuit Current
I_OH = -2mA
I_OL = 2mA
I_CL = −18 mA
V_IN = 0.4V, 2.5V, or V_DD33
V_OUT = 0V
(Note 6)
2.0
GND
V_DD
V
0.8
V
2.7 3.2
V
0.3V V
-0.9 −1.5 V
-40
40
μA
-45
mA
SMBus Electrical Specifications
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 5)
Symbol
Parameter
Conditions
Min Typ
V_SIL
V_SIH
V_SDD
I_SLEAKB
I_SLEAKP
C_SI
Data, Clock Input Low Voltage
Data, Clock Input High Voltage
Nominal Bus Voltage
Input Leakage Per Bus Segment
Input Leakage Per Pin
Capacitance for SDA and SCK
SCK and SDA pins
2.1
2.375
±200
±10
10
Max
0.8
V_SDD
3.465
Units
V
V
V
µA
µA
pF
SMBus Timing Specifications
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 5)
Symbol
Parameter
Conditions
Min Typ
f_SMB
Bus Operating Frequency
10
t_BUF
Bus free time between top and start condition
4.7
t_HD:STA Hold time after (repeated) start condition. After this
4.0
period, the first clock is generated
t_SU:STA Repeated Start Condition Setup Time
(Note 3)
4.7
t_HD:DAT Data Hold Time
300
t_SU:DAT Data Setup Time
(Note 3)
250
t_LOW
Clock Low Time
4.7
t_HIGH
Clock High Time
4.0
t_SU:CS
SMB_CS Setup Time
(Note 3)
30
t_HS:CS
SMB_CS Hold Time
(Note 3)
100
t_POR
Time in which the device must be operational after (Note 3)
power on
Max Units
100 kHz
μs
µs
µs
ns
ns
µs
50
µs
ns
ns
500 ms
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