DP8212 Datasheet, PDF (6/10 Pages) National Semiconductor (TI) – 8-Bit Input/Output Port

Logic Tables
Logic Table A
STB
MD
(DS₁DS₂)
Data Out
Equals
0
0
0
TRI-STATE
1
0
0
TRI-STATE
0
1
0
DATA LATCH
1
1
0
DATA LATCH
0
0
1
DATA LATCH
1
0
1
DATA IN
0
1
1
DATA IN
1
1
1
DATA IN
CLR K resets data latch to the output low state
The data latch clock is level sensitive a low level clock latches the data
Logic Table B
CLR
(DS₁DS₂)
STB
Q
INT
0 RESET
0
0
0
1
1
0
0
0
1
1
0
K
1
0
1
1 RESET
0
0
0
1
0
0
0
1
Internal Service Request flip-flop
Functional Pin Definitions
The following describes the function of all the DP8212
DP8212M input output pins Some of these descriptions
reference internal circuits
INPUT SIGNALS
Device Select (DS₁ DS₂) When DS₁ is low and DS₂ is
high the device is selected The output buffers are enabled
and the service request flip-flop is asynchronously reset
(cleared) when the device is selected
Mode (MD) When high (output mode) the output buffers
are enabled and the source of the data latch clock input is
the device selection logic (DS₁  DS₂) When low (input
mode) the state of the output buffers is determined by the
device selection logic (DS₁  DS₂) and the source of the
data latch clock input is the strobe (STB) input
Strobe (STB) Used as data latch clock input when the
mode (MD) input is low (input mode) Also used to synchro-
nously set the service request flip-flop which is negative
edge triggered
Data In (DI₁ – DI₈) Eight-bit data input to the data latch
which consists of eight D-type flip-flops Incorporating a lev-
el sensitive clock while the data latch clock input is high the
Q output of each flip-flop follows the data input When the
clock input returns low the data latch stores the data input
The clock input high overrides the clear (CLR) input data
latch reset
Clear (CLR) When low asynchronously resets (clears) the
data latch and the service request flip-flop The service re-
quest flip-flop is in the non-interrupting state when reset
OUTPUT SIGNALS
Interrupt (INT) Goes low (interrupting state) when either
the service request flip-flop is synchronously set by the
strobe (STB) input or the device is selected
Data Out (DO₁ – DO₈) Eight-bit data output of data buffers
which are TRI-STATE non-inverting stages These buffers
have a common control line that either enables the buffers
to transmit the data from the data latch outputs or disables
the buffers by placing them in the high-impedance state
Connection Diagram
Dual-In-Line Package
Top View
TL F 6824 – 6
Order Number DP8212J DP8212N
or DP8212MJ
See NS Package Number J24A or N24A
6