DC89C386 Datasheet, PDF (6/10 Pages) National Semiconductor (TI) – Twelve Channel CMOS Differential Line Receiver

Application Information (Continued)
gation delay measurements (see Figures 5, 6). Differential
skew is calculated from t_PHLD and t_PLHD differential propa-
gation delay measurements (see Figures 7, 8).
(Circuit 1)
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(Circuit 2)
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FIGURE 5. Circuits for Measuring Single-Ended Propagation Delays (See Figure 6)
Waveforms for Circuit 1
Waveforms for Circuit 2
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FIGURE 6. Propagation Delay Waveforms for Circuit 1 and Circuit 2 (See Figure 5)
In Figure 6, VX, where X is a number, is the waveform
voltage level at which the propagation delay measurement
either starts or stops. Furthermore, V1 and V2 are normally
identical. The same is true for V3 and V4. However, as
mentioned before, these levels are not standardized and
may vary, even with similar devices from other companies.
Also note, V_REF in Figure 1 should equal V1 and V2 in Figure
6.
The single-ended skew provides information about the pulse
width distortion of the output waveform. The lower the skew,
the less the output waveform will be distorted. For best case,
skew would be zero, and the output duty cycle would be
50%, assuming the input has a 50% duty cycle.
Waveforms for Circuit 3
(Circuit 3)
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FIGURE 7. Circuit for Measuring Differential
Propagation Delays (See Figure 8)
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FIGURE 8. Propagation Delay Waveforms
for Circuit 3 (see Figure 7)
For differential propagation delays, V1 may not equal V2.
Furthermore, the crossing point of RI and RI* corresponds to
zero volts on the differential waveform. (See middle wave-
form in Figure 8.) This is true whether V1 equals V2 or not.
However, if V1 and V2 are specified voltages, then V1 and
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