CLC425 Datasheet, PDF (6/9 Pages) National Semiconductor (TI) – Ultra Low Noise Wideband Op Amp

As seen in Figure 5, e_ni is dominated by the intrinsic
voltage noise (e_n) of the amplifier for equivalent source
resistances below 33.5Ω. Between 33.5Ω and 6.43kΩ,
e_ni is dominated by the thermal noise (e_t = _{4kTR seq}) of
the external resistors. Above 6.43kΩ, e_ni is dominated by
the amplifier's current noise ( 2i_nR_seq ). The point at
which the CLC425's voltage noise and current noise
contribute equally occurs for R_seq=464Ω (i.e. e_n / 2i_n ).
As an example, configured with a gain of +20V/V giving
a -3dB of 90MHz and driven from an R_seq=25Ω, the
CLC425 produces a total equivalent input noise voltage
(_{eni∗ 1.57∗90MHz} ) of 16.5µV_rms.
The noise figure is related to the equivalent source
resistance (R_seq) and the parallel combination of R_f and
R_g. To minimize noise figure, the following steps are
recommended:
• Minimize R_f||R_g
• Choose the optimum R_s (R_OPT)
R_OPT is the point at which the NF curve reaches a
minimum and is approximated by:
R_OPT ≅ (e_n/i_n)
Figure 6 is a plot of NF vs R_s with R_f||R_g = 9.09 (A_v = +10).
The NF curves for both Unterminated and Terminated
systems are shown. The Terminated curve assumes R_s
= R_T. The table indicates the NF for various source
resistances including R_s = R_OPT.
Figure 5: Voltage Noise Density vs. Source Resistance
If bias current cancellation is not a requirement, then
R_f||R_g does not need to equal R_seq. In this case, according
to Equation 1, R_f||R_g should be as low as possible in
order to minimize noise. Results similar to Equation 1
are obtained for the inverting configuration of Figure 2 if
R_seq is replaced by R_b and R_g is replaced by R_g+R_s. With
these substitutions, Equation 1 will yield an e_ni refered to
the non-inverting input. Refering e_ni to the inverting input
is easily accomplished by multiplying e_ni by the ratio of
non-inverting to inverting gains.
Noise Figure
Noise Figure (NF) is a measure of the noise degradation
caused by an amplifier.
Figure 6: Noise Figure vs Source Resistance
Supply Current Adjustment
The CLC425's supply current can be externally adjusted
downward from its nominal value by adding an optional
resistor (R_p) between pin 8 and the negative supply as
shown in Figure 7. Several of the plots found within the plot
pages demonstrate the CLC425’s behavior at different
supply currents. The plot labeled “I_cc vs. R_p” provides the
means for selecting R_p and shows the result of standard IC
process variation which is bounded by the 25°C curve.
+Vcc
NF
=
10LOG


S_i
S_o
/
/
N_i
N_o


=
10LOG


e_ni ²
e_t ²


The Noise Figure formula is shown in Equation 3. The
addition of a terminating resistor R_T, reduces the
external thermal noise but increases the resulting NF.
The NF is increased because R_T reduces the input signal
amplitude thus reducing the input SNR.
( ) ( ) _NF
=
10LOG



e_n ²
+
i_n
2


R_seq
+

R_f | | R_g
2_

+ 4kTR_seq
+ 4kT
4kTR_seq
R_f | | R_g




Rseq = Rs for Unterminated Systems
Rseq = Rs II RT for Terminated Systems
Equation 3: Noise Figure Equation
3
7
CLC425 ⁶
2
8
4
Rp
Vout
-Vcc
Figure 7: External Supply Current Adjustment
Non-Inverting Gains Less Than 10V/V
Using the CLC425 at lower non-inverting gains requires
external compensation such as the shunt compensation
as shown in Figure 8. The quiescent supply current must
also be reduced to 5mA with R_p for stability. The com-
pensation capacitors are chosen to reduce frequency
response peaking to less than 1dB. The plot in the
"Typical Performance" section labeled “Differential Gain
and Phase” shows the video performance of the CLC425
with this compensation circuitry.
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