ADC08D1020 Datasheet, PDF (6/44 Pages) National Semiconductor (TI) – Low Power, 8-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter

Pin Functions
Pin No.
Symbol
7
V_CMO
31
V_BG
126
CalRun
Equivalent Circuit
Description
Common Mode Voltage. This pin is the common mode
output in d.c. coupling mode and also serves as the a.c.
coupling mode select pin. When d.c. coupling is used, the
voltage output at this pin is required to be the common mode
input voltage at V_IN+ and V_IN− when d.c. coupling is used.
This pin should be grounded when a.c. coupling is used at
the analog inputs. This pin is capable of sourcing or sinking
100 μA. See 2.2 THE ANALOG INPUT.
Bandgap output voltage capable of 100 μA source/sink and
can drive a load up to 80 pF.
Calibration Running indication. This pin is at a logic high
when calibration is running.
32
R_EXT
34
Tdiode_P
35
Tdiode_N
41
ECE
52
DRST_SEL
External bias resistor connection. Nominal value is 3.3 kΩ
(±0.1%) to ground. See 1.1.1 Calibration.
Temperature Diode Positive (Anode) and Negative
(Cathode). These pins may be used for die temperature
measurements, however no specified accuracy is implied or
guaranteed. Noise coupling from adjacent output data
signals has been shown to affect temperature
measurements using this feature. See 2.6.2 Thermal
Management.
Extended Control Enable. This pin always enables and
disables Extended Control Enable. When this pin is set logic
high, the extended control mode is inactive and all control of
the device must be through control pins only . When it is set
logic low, the extended control mode is active. This pin
overrides the Extended Control Enable signal set using pin
14.
DCLK_RST select. This pin selects whether the DCLK is
reset using a single-ended or differential signal. When this
pin is floating or logic high, the DCLK_RST operation is
single-ended and pin 14 functions as FSR/ALT_ECE. When
this pin is logic low, the DCLK_RST operation becomes
differential with functionality on pin 15 (DCLK_RST+) and pin
14 (DCLK_RST-). When in differential DCLK_RST mode,
there is no pin-controlled FSR and the full-scale-range is
defaulted to the higher V_IN input level. When pin 41 is set
logic low, the extended control mode is active and the Full-
Scale Voltage Adjust registers can be programmed.
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