DP83901A Datasheet, PDF (53/62 Pages) National Semiconductor (TI) – Serial Network Interface Controller

15 0 Switching Characteristics AC Specs DP83901A Note All Timing is Preliminary (Continued)
DMA Address Generation
TL F 10469 – 37
Symbol
Parameter
Min
Max
Units
bcyc
Bus Clock Cycle Time (Note 2)
50
125
ns
bch
Bus Clock High Time
20
ns
bcl
Bus Clock Low Time
20
ns
bcash
Bus Clock to Address Strobe High
34
ns
bcasl
Bus Clock to Address Strobe Low
44
ns
aswo
Address Strobe Width Out
bch
ns
bcadv
Bus Clock to Address Valid
45
ns
bcadz
Bus Clock to Address TRI-STATE (Note 3)
15
55
ns
ads
Address Setup to ADS0 1 Low
bch b 15
ns
adh
Address Hold from ADS0 1 Low
bcl b 5
ns
Note 1 Cycles T1 T2 T3 and T4 are only issued for the first transfer in a burst when 32-bit mode has been selected
Note 2 The rate of bus clock must be high enough to support transfers to from the FIFO at a rate greater than the serial network transfers from to the FIFO
Note 3 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with
no contention
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