DP83955A Datasheet, PDF (51/54 Pages) National Semiconductor (TI) – LitE Repeater Interface Controller

11 0 AC Timing Test Conditions
All specifications are valid only if the mandatory isolation is
employed and all differential signals are taken to be at AUI
side of the pulse transormer
Input Pulse Levels (TTL CMOS)
GND to 3 0V
Input Rise and Fall Times (TTL CMOS)
5 ns
Input and Output Reference Levels (TTL CMOS)
1 5V
Input Pulse Levels (Diff )
b350 mV to b1315 mV
Input and Output Reference
Levels (Diff )
50% Point of the Differential
TRI-STATE Reference Levels
Float (DV) g0 5V
Output Load (See Figure Below)
Note 1 100 pF include scope and jig capacitance
Note 2 S1 e Open for timing tests for push pull outputs
S1 e V_CC for V_OL test
S1 e GND for V_OH test
S1 e V_CC for High Impedance to active low and active low to High Impedance measurements
S1 e GND for High Impedance to active high and active high to High Impedance measurements
Capacitance T_A e 25 C f e 1 MHz
Symbol
Parameter
Typ
Units
C_IN
Input Capacitance
7
pF
C_OUT
Output Capacitance
7
pF
Derating Factor
Output timings are measured with a purely capacitive load
for 50 pF The following correction factor can be used for
other loads C_L ^t 50 pF a 0 3 ns pF
TL F 11240 – 42
TL F 11240 – 43
Note In the above diagram the TX^a and TX^b signals are taken from the
AUI side of the isolation (pulse transformer) The pulse transformer used for
all testing is the Pulse Engineering PE64103
51