DP83816 Datasheet, PDF (50/106 Pages) National Semiconductor (TI) – DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPHYTER-II)

4.0 Register Set (Continued)
4.2.12 Receive Descriptor Pointer Register
This register points to the current Receive Descriptor.
Tag: RXDP
Offset: 0030h
Size: 32 bits
Access: Read Write
Hard Reset: 00000000h
Soft Reset: 00000000h
Bit
31-2
1-0
Bit Name
RXDP
Description
Receive Descriptor Pointer
The current value of the receive descriptor pointer. When the receive state machine is idle, software must
set RXDP to the address of an available receive descriptor. While the receive state machine is active,
RXDP will follow the state machine as it advances through a linked list of available descriptors. If the link
field of the current receive descriptor is NULL (signifying the end of the list), RXDP will not advance, but
will remain on the current descriptor. Any subsequent writes to the RXE bit of the CR register will cause
the receive state machine to reread the link field of the current descriptor to check for new descriptors
that may have been appended to the end of the list. Software should not write to this register unless the
receive state machine is idle. Receive descriptors must be aligned on 32-bit boundaries (A1-A0 must be
zero). A 0 written to RXDP followed by a subsequent write to RXE will cause the receiver to enter silent
RX mode, for use during WOL. In this mode packets will be received and buffered in FIFO, but no DMA
to system memory will occur. The packet data may be recovered from the FIFO by writing a valid
descriptor address to RXDP and then strobing RXE.
unused
50
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