SM72295 Datasheet, PDF (5/12 Pages) National Semiconductor (TI) – Photovoltaic Full Bridge Driver

Symbol Parameter
Conditions
LO & HO GATE DRIVER
V_OL
V_OH
I_OHL
I_OLL
t_LPHL
t_LPLH
t_HPHL
Low-Level Output Voltage
High-Level Output Voltage
Peak Pullup Current
I_LO = 100mA
V_OL = LO-PGND or HO-HS
I_LO = -100mA
V_OH = VCC-LO or VCC-HO
HO, LO = 12V
Peak Pulldown Current
HO, LO = 0V
LO Turn-Off Propagation Delay LI Falling to LO Falling
LO Turn-On Propagation Delay LI Rising to LO Rising
HO Turn-Off Propagation
Delay
HI Falling to HO Falling
t_HPLH
t_MON
LO Turn-On Propagation Delay HI Rising to HO Rising
Delay Matching: LO on & HO
off
t_MOFF
Delay Matching: LO off & HO
on
t_RC, t_FC
t_PW
Either Output Rise/Fall Time
Minimum Input Pulse Width
that Changes the Output
C_L = 1000pF
t_BS
Bootstrap Diode Turn-On or
Turn-Off Time
I_F = 100mA/ I_R = 100mA
CURRENT SENSE AMPLIFIER
V_OS
Offset voltage
R_SI = R_SO = 500, 10mV sense
resistor voltage
Gain is programmed with
5mV sense resistor voltage
Gain 5mV
external resistors
IOUT, IIN =(RL/RSI )* (SI-SO)
R_SI = R_SO = 1000, R_L = 75K
Gain
50mV
Gain is programmed with
50mV sense resistor voltage
external resistors
IOUT, IIN =(RL/RSI )* (SI-SO)
R_SI = R_SO = 1000, R_L = 75K
Vclamp Output Clamp
CURRENT SENSE BUFFER
0.1V sense resistor voltage
R_SI = R_SO = 1000, R_L = 75K
Offset voltage (BIN-IIN),
(BOUT-IOUT)
IIN = 2.5V
Output low voltage BOUT,BIN IIN, IOUT = 0
Output high voltage BOUT,BIN IIN, IOUT = VDD
THERMAL RESISTANCE
θ_JA
Junction to Ambient
SOIC-28 (Note 3)
Min
Typ
Max
0.16
0.4
0.28
0.6
3
3
22
26
22
26
1
1
8
50
37
-2
2
390
3.85
VDD
-60
0
VDD-100mV VDD-30mV
60
50
VDD
60
Units
V
V
A
A
ns
ns
ns
ns
ns
ns
ns
ns
ns
mV
mV
V
V
mV
mV
mV
°C/W
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. 2 kV for all pins except HB, HO & HS which are rated
at 1000V.
Note 3: 2 layer board with 2 oz Cu using JEDEC JESD51 thermal board.
Note 4: Min and Max limits are 100% production tested at 25ºC. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 5: In the application the HS nodes are clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not exceed –1V.
However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur,
the HS voltage must never be more negative than VCC-15V. For example if VCC = 10V, the negative transients at HS must not exceed –5V.
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