SCAN12100 Datasheet, PDF(5/14 Page) National Semiconductor (TI) – 1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement

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SCAN12100 Datasheet, PDF (5/14 Pages) National Semiconductor (TI) – 1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement

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Pin #

Pin Name

SPMODE [0]

SPMODE [1]

98 TENBMODE

99 LOOP [0]

100 LOOP [1]

MDC/MDIO

30 MDC

31 MDIO

37 ADD0

36 ADD1

35 ADD2

34 ADD3

33 ADD4

IEEE 1149.1 (JTAG)

45 TDI

41 TDO

44 TMS

43 TCK

46 TRSTB

RESERVED PINS

83 RES1

84 RES2

POWER

9, 15, 20, AVDD18

32, 38, 47,

8, 14, 21, AVDD33

1, 2, 28, 29 PVDD33

50, 51, 76, IOVDD

GROUND

3, 4, 5, 10, GND

13, 16, 19,

24, 25, 26,

27, 39, 40,

48, 49, 63,

75, 86

I/O, Type

Description

I, LVTTL or 1.8V Speed mode configuration. (OPMODE must be low)

LVCMOS Internal Pulling both pins low enables MDIO control.

pull down

SPMODE [1] SPMODE [0]

Rate selected via MDIO

614.4 Mbps rate mode

1228.8 Mbps rate mode

Reserved

I, LVTTL or 1.8V Enable 10-bit mode

LVCMOS, Internal The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2

pull down

0 = Selects 8-bit mode. Enables the internal 8b/10b encoder and decoder.

1 = Selects 10-bit mode. Bypasses internal 8b/10b encoder and decoder.

I, LVTTL or 1.8V Loop back configuration.

LVCMOS, Internal Pulling both pins low enables MDIO control.

pull down

Note: During Special line (remote) loop back mode, the output de-emphasis control

is disabled.

LOOP [1]

LOOP [0]

Normal modeâno loop back

Line (remote) loop back mode

Local loop back mode

Special line (remote) loop back mode

3.3V LVTTL MDC/MDIO configuration bus.

Internal pull up on Protocol per IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL

ADDR pins compatible, not 1.2V signal compatible.

3.3V LVTTL JTAG test bus for IEEE 1149.1 and 1149.6 support.

Internal pull up on

TDI, TMS, and

TRSTB

I, Power

Reserved.

Tie with 5 Kâ¦ resistor to ground.

1.8V analog supply.

I, Power

I, Ground

3.3V analog supply.

3.3V PLL supply (minimize supply noise to < 100 mV peak-to-peak).

1.8V or 3.3V parallel I/O bus and control pin supply.

See VSEL pin description for additional information.

Device ground.

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