MF10 Datasheet, PDF (5/20 Pages) National Semiconductor (TI) – Universal Monolithic Dual Switched Capacitor Filter

Typical Performance Characteristics (Continued)
f_CLK f_O Deviation
vs Clock Frequency
f_CLK f_O Deviation
vs Clock Frequency
Deviation of ^fCLK
vs Nominal Q ^fO
Deviation of ^fCLK
vs Nominal Q ^fO
Pin Descriptions
LP(1 20) BP(2 19) The second order lowpass bandpass
N AP HP(3 18) and notch allpass highpass outputs
These outputs can typically sink 1 5 mA
and source 3 mA Each output typically
swings to within 1V of each supply
INV(4 17)
The inverting input of the summing op-
amp of each filter These are high im-
pedance inputs but the non-inverting in-
put is internally tied to AGND making
INV_A and INV_B behave like summing
junctions (low impedance current in-
puts)
S1(5 16)
S1 is a signal input pin used in the all-
pass filter configurations (see modes 4
and 5) The pin should be driven with a
source impedance of less than 1 kX If
S1 is not driven with a signal it should be
tied to AGND (mid-supply)
TL H 10399 – 3
S_{A B}(6)
This pin activates a switch that connects
one of the inputs of each filter’s second
summer to either AGND (S_{A B} tied to
V^b) or to the lowpass (LP) output (S_{A B}
tied to V^a) This offers the flexibility
needed for configuring the filter in its
various modes of operation
V_A^a(7) V_D^a(8)
Analog positive supply and digital posi-
tive supply These pins are internally
connected through the IC substrate and
therefore V_A^a and V_D^a should be de-
rived from the same power supply
source They have been brought out
separately so they can be bypassed by
separate capacitors if desired They
can be externally tied together and by-
passed by a single capacitor
V_A^b(14) V_D^b(13) Analog and digital negative supplies
The same comments as for V_A^a and
V_D^a apply here
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