LV8572A Datasheet, PDF (5/20 Pages) National Semiconductor (TI) – LV8572A Low Voltage Real Time Clock (RTC)

General Description (Continued)
The LV8572A’s interrupt structure provides three basic
types of interrupts Periodic Alarm Compare and Power
Fail Interrupt mask and status registers enable the masking
and easy determination of each interrupt
Pin Description
CS RD WR (Inputs) These pins interface to mP control
lines The CS pin is an active low enable for the read and
write operations Read and Write pins are also active low
and enable reading or writing to the RTC All three pins are
disabled when power failure is detected However if a read
or write is in progress at this time it will be allowed to com-
plete its cycle
A0 – A4 (Inputs) These 5 pins are for register selection
They individually control which location is to be accessed
These inputs are disabled when power failure is detected
OSC IN (Input) OSC OUT (Output) These two pins are
used to connect the crystal to the internal parallel resonant
oscillator The oscillator is always running when power is
applied to V_BB and V_CC and the correct crystal select bits in
the Real Time Mode Register have been set
MFO (Output) The multi-function output can be used as a
second interrupt output for interrupting the mP This pin can
also provide an output for the oscillator The MFO output is
configured as push-pull active high for normal or single
power supply operation and as an open drain during stand-
by mode (V_BB ^l V_CC) If in battery backed mode and a pull-
up resistor is attached it should be connected to a voltage
no greater than V_BB
INTR (Output) The interrupt output is used to interrupt the
processor when a timing event or power fail has occurred
and the respective interrupt has been enabled The INTR
output is permanently configured active low open drain If in
battery backed mode and a pull-up resistor is attached it
should be connected to a voltage no greater than V_BB
D0 – D7 (Input Output) These 8 bidirectional pins connect
to the host mP’s data bus and are used to read from and
write to the RTC When the PFAIL pin goes low and a write
is not in progress these pins are at TRI-STATE
PFAIL (Input) In battery backed mode this pin can have a
digital signal applied to it via some external power detection
logic When PFAIL e logic 0 the RTC goes into a lockout
mode in a minimum of 30 ms or a maximum of 63 ms unless
lockout delay is programmed In the single power supply
mode this pin is not useable as an input and should be tied
to V_CC Refer to section on Power Fail Functional Descrip-
tion
V_BB (Battery Power Pin) This pin is connected to a back-
up power supply This power supply is switched to the inter-
nal circuitry when the V_CC becomes lower than V_BB Utiliz-
ing this pin eliminates the need for external logic to switch in
and out the back-up power supply If this feature is not to be
used then this pin must be tied to ground the RTC pro-
grammed for single power supply only and power applied to
the V_CC pin
V_CC This is the main system power pin
GND This is the common ground power pin for both V_BB
and V_CC
Connection Diagrams
In-Line Packages
Top View
TL F 11417 – 5
DIP Order Number LV8572AN
See NS Package Number N24C
SOIC Order Number LV8572AM
See NS Package Number M24B
Plastic Chip Carrier
Top View
Order Number LV8572AV
See NS Package Number V28A
TL F 11417 – 6
5