LP3942 Datasheet, PDF (5/20 Pages) National Semiconductor (TI) – The Dual RGB LED Controller with 1.5x/2x Charge Pump and SPI Interface

Logic Interface Characteristics (1.8V Logic)
Symbol
Parameter
LOGIC INPUTS
V_IL
Input Low Level
V_IH
Input High Level
I_H
Logic Input Current
f_SPI
t_NRST
Interface Clock
Reset Pulse Width
Conditions
SS, SI, SCK, NRST
SS, SI, SCK, NRST
SS, SI, SCK
NRST (1 MΩ pull-down)
NRST
Limit
Units
Min
Typ
Max
0.5
V
1.2
V
−1
1
µA
−1
3
µA
10
MHz
50
µs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pins.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J = 160˚C (typ.) and disengages at T_J =
140˚C (typ.).
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe
Package (LLP).
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin. MIL-STD-883 3015.7
Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP = 105˚C), the maximum power
dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ_JA), as given by the
following equation: T_A-MAX = T_J-MAX-OP − (θ_JA x P_D-MAX).
Note 7: Junction-to-ambient thermal resistance (θ_JA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC
standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array of thermal vias. The ground plane on the board
is 50 mm x 50 mm. Thickness of copper layers are 36 µm/18 µm/18 µm/36 µm (1.5 oz/1 oz/1 oz/1.5 oz). Ambient temperature in simulation is 22˚C, still air. Power
dissipation is 1W.
The value of θ_JA of the LP3942 in LLP-24 could vary widely, depending on PWB material, layout, and environmental conditions. In applications where high maximum
power dissipation exists (high V_IN, high I_OUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to
Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet.
Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 9: C_IN, C_OUT, C1, and C2 : Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Minimum capacitance value for
C_IN, C₁, and C₂ capacitors is 70% of nominal value. This tolerance includes manufacturing tolerance, temperature coefficient and voltage dependency (roll-off). C_OUT
minimum effective capacitance value is 3.0 µF.
Note 10: Output voltage accuracy does not include V_DD (2.78V supply voltage) tolerance.
Note 11: The quiescent current does not include the current setting resistors’ current.
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