LP3878 Datasheet, PDF (5/11 Pages) National Semiconductor (TI) – Micropower 800mA Low Noise Ceramic Stable Voltage Regulator for Low Voltage Applications Designed for Use with Very Low ESR Output Capacitors

Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the
device outside of its rated operating conditions.
Note 2: ESD testing was performed using Human Body Model, a 100 pF capacitor discharged through a 1.5 kΩ resistor. The ESD rating of pin 8 is 1kV.
Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, T_J(MAX), the junction-to-ambient thermal resistance, θ_J−A,
and the ambient temperature, T_A. The maximum allowable power dissipation at any ambient temperature is calculated using:
The value θ_J−A for the LLP (SD) package is specifically dependent on PCB trace area, trace material, and the number of layers and thermal vias. For improved
thermal resistance and power dissipation for the LLP package, refer to Application Note AN-1187. Exceeding the maximum allowable power dissipation will cause
excessive die temperature, and the regulator will go into thermal shutdown.
Note 4: If used in a dual-supply system where the regulator load is returned to a negative supply, the LP3878 output must be diode-clamped to ground.
Note 5: The output PNP structure contains a diode between the V_IN and V_OUT terminals that is normally reverse-biased. Forcing the output above the input will turn
on this diode and may induce a latch-up mode which can damage the part (see Application Hints).
Note 6: Limits are guaranteed through testing, statistical correlation, or design.
Note 7: Typical numbers reperesent the most likely parametric norm for 25˚C operation.
Note 8: See Typical Performance Characteristics curves.
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