LF13006 Datasheet, PDF (5/8 Pages) National Semiconductor (TI) – Digital Gain Set

Application Information
FLOW-THROUGH OPERATION
THE LF13006 LF13007 can be operated with control lines
CS and WR grounded In this mode new data on the digital
inputs will immediately set the new gain value Input data
cannot be latched in this mode
INPUT CURRENT
Current flowing through the input (pin 2) due to bias current
of the op amp will result in a gain error due to switch imped-
ance Normally this error is very small For example 10 nA
of bias current flowing through 3 kX of switch resistance will
result in an error of 30 mV at the summing node However
applications that have significant current flowing through the
input must take this effect into account
SETTLING TIME
Settling time is a function of the particular op amp used with
the LF13006 7 and the gain that is selected It can be opti-
mized and stability problems can be prevented through the
use of a lead capacitor from the inverting input to the output
of the amplifier A lead capacitor is effective whenever the
feedback around an amplifier is resistive whether with dis-
crete resistors or with the LF13006 7 It compensates for
the feedback pole created by the parallel resistance and
capacitance from the inverting input of the op amp to AC
ground
Settling Time Test Circuit
TL H 5114 – 6
Typical Settling Time Curves
Unstable at C_L less than 2 pF
Typical Applications
Variable Capacitance Multiplier
C_effective e C1(gain set )
Note Output swing at input op amp
is multiplied by set gain Signal
range may be limited
TL H 5114 – 7
Variable Time Constant Filter
R
Time constant e C1
N
N e setting of LF13006
1
(range e to 1)
128
TL H 5114 – 8
5
TL H 5114 – 9