DS90LV031B_05 Datasheet, PDF (5/9 Pages) National Semiconductor (TI) – 3V LVDS Quad CMOS Differential Line Driver

Parameter Measurement Information (Continued)
Typical Application
FIGURE 5. Driver TRI-STATE Delay Waveform
10131107
FIGURE 6. Point-to-Point Application
10131108
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-001), AN808,
AN977, AN971, AN916, AN805, AN903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 6. This configuration provides a clean signaling
environment for the quick edge rates of the drivers. The
receiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically, the characteristic
differential impedance of the media is in the range of 100Ω.
A termination resistor of 100Ω should be selected to match
the media, and is located as close to the receiver input pins
as possible. The termination resistor converts the current
sourced by the driver into a voltage that is detected by the
receiver. Other configurations are possible such as a multi-
receiver configuration, but the effects of a mid-stream con-
nector(s), cable stub(s), and other impedance discontinuities
as well as ground shifting, noise margin limits, and total
termination loading must be taken into account.
The DS90LV031B differential line driver is a balanced cur-
rent source design. A current mode driver, generally speak-
ing has a high output impedance and supplies a constant
current for a range of loads (a voltage mode driver on the
other hand supplies a constant voltage for a range of loads).
Current is switched through the load in one direction to
produce a logic state and in the other direction to produce
the other logic state. The output current is typically 3.5 mA, a
minimum of 2.5 mA, and a maximum of 4.5 mA. The current
mode requires (as discussed above) that a resistive termi-
nation be employed to terminate the signal and to complete
the loop as shown in Figure 6. AC or unterminated configu-
rations are not allowed. The 3.5 mA loop current will develop
a differential voltage of 350 mV across the 100Ω termination
resistor which the receiver detects with a 250 mV minimum
differential noise margin neglecting resistive line losses
(driven signal minus receiver threshold (350 mV – 100 mV =
250 mV)). The signal is centered around +1.2V (Driver Off-
set, V_OS) with respect to ground as shown in Figure 7. Note
that the steady-state voltage (V_SS) peak-to-peak swing is
twice the differential voltage (V_OD) and is typically 700 mV.
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quies-
cent current remains relatively flat versus switching fre-
5
www.national.com