DS90LV031A Datasheet, PDF (5/11 Pages) National Semiconductor (TI) – 3V LVDS Quad CMOS Differential Line Driver

Parameter Measurement Information (Continued)
Typical Application
FIGURE 5. Driver TRI-STATE Delay Waveform
DS100095-7
DS100095-8
FIGURE 6. Point-to-Point Application
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-001), AN808,
AN1035, AN977, AN971, AN916, AN805, AN903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 6. This configuration provides a clean signaling en-
vironment for the quick edge rates of the drivers. The re-
ceiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically, the characteristic dif-
ferential impedance of the media is in the range of 100Ω. A
termination resistor of 100Ω should be selected to match the
media, and is located as close to the receiver input pins as
possible. The termination resistor converts the current
sourced by the driver into a voltage that is detected by the re-
ceiver. Other configurations are possible such as a
multi-receiver configuration, but the effects of a mid-stream
connector(s), cable stub(s), and other impedance disconti-
nuities as well as ground shifting, noise margin limits, and to-
tal termination loading must be taken into account.
The DS90LV031A differential line driver is a balanced cur-
rent source design. A current mode driver, generally speak-
ing has a high output impedance and supplies a constant
current for a range of loads (a voltage mode driver on the
other hand supplies a constant voltage for a range of loads).
Current is switched through the load in one direction to pro-
duce a logic state and in the other direction to produce the
other logic state. The output current is typically 3.5 mA, a
minimum of 2.5 mA, and a maximum of 4.5 mA. The current
mode requires (as discussed above) that a resistive termi-
nation be employed to terminate the signal and to complete
the loop as shown in Figure 6. AC or unterminated configu-
rations are not allowed. The 3.5 mA loop current will develop
a differential voltage of 350 mV across the 100Ω termination
resistor which the receiver detects with a 250 mV minimum
differential noise margin neglecting resistive line losses
(driven signal minus receiver threshold (350 mV – 100 mV =
250 mV)). The signal is centered around +1.2V (Driver Off-
set, V_OS) with respect to ground as shown in Figure 7. Note
that the steady-state voltage (V_SS) peak-to-peak swing is
twice the differential voltage (V_OD) and is typically 700 mV.
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quies-
cent current remains relatively flat versus switching fre-
quency. Whereas the RS-422 voltage mode driver increases
exponentially in most case between 20 MHz–50 MHz. This
is due to the overlap current that flows between the rails of
the device when the internal gates switch. Whereas the cur-
rent mode driver switches a fixed current between its output
without any substantial overlap current. This is similar to
some ECL and PECL devices, but without the heavy static
I_CC requirements of the ECL/PECL designs. LVDS requires
> 80% less current than similar PECL devices. AC specifica-
tions for the driver are a tenfold improvement over other ex-
isting RS-422 drivers.
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