DS90LV004_07 Datasheet, PDF (5/12 Pages) National Semiconductor (TI) – 4-Channel LVDS Buffer/Repeater with Pre-Emphasis

Symbol
Parameter
Conditions
LVDS OUTPUT DC SPECIFICATIONS (OUTn±)
V_OD
ΔV_OD
Differential Output Voltage,
0% Pre-emphasis (Note 5)
Change in V_OD between
Complementary States
R_L = 100Ω external resistor between OUT+ and
OUT−
V_OS
ΔV_OS
Offset Voltage (Note 6)
Change in V_OS between
Complementary States
I_OS
Output Short Circuit Current
C_OUT2 Output Capacitance
SUPPLY CURRENT (Static)
OUT+ or OUT− Short to GND
OUT+ or OUT− to GND when TRI-STATE
I_CC
Supply Current
All inputs and outputs enabled and active,
terminated with differential load of 100Ω between
OUT+ and OUT-, 0% pre-emphasis
I_CCZ
Supply Current - Power Down PWDN = L, 0% pre-emphasis
Mode
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
t_LHT
Differential Low to High
Transition Time
t_HLT
Differential High to Low
Transition Time
Use an alternating 1 and 0 pattern at 200 Mbps,
measure between 20% and 80% of V_OD. (Note
11)
t_PLHD
t_PHLD
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Use an alternating 1 and 0 pattern at 200 Mbps,
measure at 50% V_OD between input to output.
t_SKD1
t_SKCC
Pulse Skew
|t_PLHD–t_PHLD| (Note 11)
Output Channel to Channel Skew Difference in propagation delay (t_PLHD or t_PHLD)
among all output channels. (Note 11)
t_SKP
Part to Part Skew
Common Edge, parts at same temp and V_CC (Note
11)
t_JIT
Jitter (0% Pre-emphasis)
(Note 7)
RJ - Alternating 1 and 0 at 750 MHz (Note 8)
DJ - K28.5 Pattern, 1.5 Gbps (Note 9)
TJ - PRBS 2²³-1 Pattern, 1.5 Gbps (Note 10)
t_ON
LVDS Output Enable Time
Time from PWDN to OUT± change from TRI-
STATE to active.
t_OFF
LVDS Output Disable Time
Time from PWDN to OUT± change from active to
TRI-STATE.
Min
250
−35
1.05
−35
Typ
(Note 4)
Max
500 600
35
1.18 1.475
35
−60 −90
5.5
117 140
2.7
6
210 300
210 300
2.0
3.2
2.0
3.2
25
80
50
125
1.1
1.1
1.5
43
62
35
85
300
12
Units
mV
mV
V
mV
mA
pF
mA
mA
ps
ps
ns
ns
ps
ps
ns
psrms
psp-p
psp-p
ns
ns
Note 4: Typical parameters are measured at V_DD = 3.3V, T_A = 25°C. They are for reference purposes, and are not production-tested.
Note 5: Differential output voltage V_OD is defined as ABS(OUT+–OUT−). Differential input voltage V_ID is defined as ABS(IN+–IN−).
Note 6: Output offset voltage V_OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Note 7: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 8: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V_ID = 500mV, 50% duty cycle at
750MHz, t_r = t_f = 50ps (20% to 80%).
Note 9: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = V_ID = 500mV, K28.5 pattern at 1.5 Gbps,
t_r = t_f = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
Note 10: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been subtracted. The input
voltage = V_ID = 500mV, 2²³-1 PRBS pattern at 1.5 Gbps, t_r = t_f = 50ps (20% to 80%).
Note 11: Not production tested. Guaranteed by a statistical analysis on a sample basis at the time of characterization.
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