DS90CR287 Datasheet, PDF (5/15 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHZ

Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 3)
CMOS/TTL High-to-Low Transition Time (Figure 3)
Receiver Input Strobe Position for Bit 0 (Figure 16)
f = 85 MHz
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 5) (Figure 17)
f = 85 MHz
RxCLK OUT Period (Figure 7)
RxCLK OUT High Time (Figure 7)
f = 85 MHz
RxCLK OUT Low Time (Figure 7)
RxOUT Setup to RxCLK OUT (Figure 7)
RxOUT Hold to RxCLK OUT (Figure 7)
RxCLK IN to RxCLK OUT Delay @ 25˚C, V_CC = 3.3V (Note 6)(Figure 9)
Receiver Phase Lock Loop Set (Figure 11)
Receiver Powerdown Delay (Figure 14)
Min
0.49
2.17
3.85
5.53
7.21
8.89
10.57
290
11.76
4
3.5
3.5
3.5
5.5
Typ
2
1.8
0.84
2.52
4.20
5.88
7.56
9.24
10.92
T
5
5
7
Max
3.5
3.5
1.19
2.87
4.55
6.23
7.91
9.59
11.27
50
6.5
6
9.5
10
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ms
µs
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows LVDS interconnect skew, inter-symbol interference
(both dependent on type/length of cable), and source clock (less than 150 ps).
Note 6: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency
for the 217/287 transmitter and 218/288A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
DS101087-2
DS101087-3
FIGURE 2. DS90CR287 (Transmitter) LVDS Output Load and Transition Times
DS101087-4
5
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