DS55451 Datasheet, PDF (5/16 Pages) National Semiconductor (TI) – Dual Peripheral Drivers

DC Test Circuits
TL F 5824–15
Both inputs are tested simultaneously
FIGURE 1 V_IH V_OL
TL F 5824 – 16
Each input is tested separately
FIGURE 2 V_IL V_OH
TL F 5824 – 17
Each input is tested separately
FIGURE 3 V_I I_IL
TL F 5824–18
Each input is tested separately
FIGURE 4 I_I I_IH
TL F 5824 – 19
Each input is tested separately
FIGURE 5 I_OS
TL F 5824 – 20
Both gates are tested simultaneously
FIGURE 6 I_CCH I_CCL
Circuit
DS55451
DS55452
DS55453
TL F 5824 – 21
DS55454
FIGURE 7 V_IH V_IL I_OH V_OL
Input
Under
Test
V_IH
V_IL
V_IH
V_IL
V_IH
V_IL
V_IH
V_IL
Other
Input
V_IH
V_CC
V_IH
V_CC
Gnd
V_IL
Gnd
V_IL
Output
Apply Measure
V_OH
I_OL
I_OL
V_OH
V_OH
I_OL
I_OL
V_OH
I_OH
V_OL
V_OL
I_OH
I_OH
V_OH
V_OL
I_OH
Note A Each input is tested separately
Note B When testing DS55453 DS75453
DS55454 DS75454 input not
under test is grounded
For all other circuits it is at 4 5V
TL F 5824 – 22
FIGURE 8 V_I V_IL
Each input is tested separately
TL F 5824 – 23
FIGURE 9 I_I I_IH
Both gates are tested simultaneously
TL F 5824 – 24
FIGURE 10 I_CCH I_CCL for AND NAND Circuits
Both gates are tested simultaneously
TL F 5824 – 25
FIGURE 11 I_CCH I_CCL for OR NOR Circuits
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