DS42MB200_07 Datasheet, PDF (5/16 Pages) National Semiconductor (TI) – Dual 4.25 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-Emphasis and Receive Equalization

Pin Name Pin Number I/O
Description
POWER
V_CC
2, 8, 14, 20, P V_CC = 3.3V ± 5%.
29, 35, 38,
Each V_CC pin should be connected to the V_CC plane through a low inductance path, typically with a
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via located as close as possible to the landing pad of the V_CC pin.
It is recommended to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each V_CC
pin to ground plane.
GND
5, 11, 17, 32, P Ground reference. Each ground pin should be connected to the ground plane through a low
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inductance path, typically with a via located as close as possible to the landing pad of the GND pin.
GND
DAP
P Die Attach Pad (DAP) is the metal contact at the bottom side, located at the center of the LLP-48
package. It should be connected to the GND plane with at least 4 via to lower the ground impedance
and improve the thermal performance of the package.
Note: I = Input, O = Output, P = Power
Functional Description
The DS42MB200 is a signal conditioning 2:1 multiplexer and
a 1:2 buffer designed to support port redundancy up to 4.25
Gbps. Each input stage has a fixed equalizer that provides
equalization to compensate about 5 dB of transmission loss
from a short backplane trace (about 10 inches backplane).
The output driver has pre-emphasis (driver-side equalization)
to compensate the transmission loss of the backplane that it
is driving. The driver conditions the output signal such that the
lower frequency and higher frequency pulses reach approxi-
mately the same amplitude at the end of the backplane, and
minimize the deterministic jitter caused by the amplitude dis-
parity. The DS42MB200 provides 4 steps of user-selectable
pre-emphasis ranging from 0, -3, -6 and –9 dB to handle dif-
ferent lengths of backplane. Figure 1 shows a driver pre-
emphasis waveform. The pre-emphasis duration is 200ps
nominal, corresponds to 0.75 bit-width at 4 Gbps. The pre-
emphasis levels of switch-side and line-side can be individu-
ally programmed.
The high speed inputs are self-biased to about 1.5V and are
designed for AC coupling. The inputs are compatible to most
AC coupling differential signals such as LVDS, LVPECL and
CML.
TABLE 1. LOGIC TABLE FOR MULTIPLEX CONTROLS
MUX_S0
0
1 (default)
MUX_S1
0
1 (default)
Mux Function
MUX_0 select switch_B input, SIB_0±.
MUX_0 select switch_A input, SIA_0±.
Mux Function
MUX_1 select switch_B input, SIB_1±.
MUX_1 select switch_A input, SIA_0±.
TABLE 2. LOGIC TABLE FOR LOOPBACK Controls
LB0A
0
1 (default)
LB0B
0
1 (default)
LB1A
0
1 (default)
LB1B
0
1 (default)
Loopback Function
Enable loopback from SIA_0± to SOA_0±.
Normal mode. Loopback disabled.
Loopback Function
Enable loopback from SIB_0± to SOB_0±.
Normal mode. Loopback disabled.
Loopback Function
Enable loopback from SIA_1± to SOA_1±.
Normal mode. Loopback disabled.
Loopback Function
Enable loopback from SIB_1± to SOB_1±.
Normal mode. Loopback disabled.
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