DS14C239 Datasheet, PDF (5/8 Pages) National Semiconductor (TI) – Dual Supply TIA/EIA-232 3 x 5 Driver/Receiver

Parameter Measurement Information (Continued)
FIGURE 5 Receiver Disable Load Circuit
TL F 11283 – 8
FIGURE 6 Receiver TRI-STATE Timing (t_PHZ t_PZH)
TL F 11283 – 9
FIGURE 7 Receiver TRI-STATE Timing (t_PLZ t_PZL)
TL F 11283 – 10
Pin Descriptions
V_CC (pin 4) Power supply pin for the device a5V
(g10%)
V^a (pin 5) Positive supply for TIA EIA-232-E drivers
Specified at 7 5V minimum and 13 2V maximum
V^b (pin 8) Negative supply for TIA EIA-232-E drivers
Recommended external capacitor C2 e 1 0 mF (16V) This
supply is not intended to be loaded externally
C1^a C1^b (pins 6 7) External capacitor connection pins
Recommended capacitor 1 0 mF (16V)
EN (pin 14) Controls the Receiver output TRI-STATE Cir-
cuit A High level on this pin will disable the Receiver Out-
put
D_IN 1 – 3 (pins 24 23 16) Driver input pins are TTL CMOS
compatible Inputs of unused drivers may be left open an
internal pull-up resistor (500 kX minimum typically 5 MX)
pulls input to V_CC Output will be LOW for open inputs
D_OUT 1 – 3 (pins 19 20 13) Driver output pins conform to
TIA EIA-232-E levels
R_IN 1 – 5 (pins 2 21 18 12 9) Receiver input pins accept
TIA EIA-232-E input voltages (g15V) Receivers feature a
noise filter and guaranteed hysteresis of 100 mV Unused
receiver input pins may be left open Internal input resistor
(5 kX) pulls input LOW providing a failsafe HIGH output
R_OUT 1 – 5 (pins 1 22 17 11 10) Receiver output pins
are TTL CMOS compatible Receiver output HIGH voltage
is specified for both CMOS and TTL load conditions
GND (pin 3) Ground pin
5
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