DAC0830 Datasheet, PDF (5/28 Pages) National Semiconductor (TI) – 8-Bit P Compatible, Double-Buffered D to A Converters

Electrical Characteristics
V_REF=10.000 V_DC unless otherwise noted. Boldface limits apply over temperature, T_MIN≤T_A≤T_MAX. For all other limits
T_A=25˚C.
Symbol Parameter
Conditions
V_CC=15.75 V_DC
See
Note
Tested
Typ
Limit
(Note 12)
(Note 5)
V_CC=12
V_DC±5% to 15
V_DC ±5%
Design Limit
(Note 6)
V_CC=4.75 V_DC
Tested
Typ
Limit
(Note 12)
(Note 5)
V_CC=5
V_DC±5%
Design
Limit
(Note 6)
AC CHARACTERISTICS
t_s
Current Setting V_IL=0V,
1.0
1.0
V_IH=5V
Time
t_W
Write and XFER V_IL=0V,
11
100
250
375
600
V_IH=5V
Pulse Width Min
9
320
320
900
900
t_DS
Data Setup Time V_IL=0V,
V_IH=5V
Min
100
250
9
375
600
320
320
900
900
t_DH
Data Hold Time V_IL=0V,
9
30
50
V_IH=5V
Min
30
50
t_CS
Control Setup
V_IL=0V,
Time
V_IH=5V
Min
110
250
9
600
900
320
320
1100
1100
t_CH
Control Hold Time V_IL=0V,
0
9
0
10
0
0
V_IH=5V
Min
0
0
Limit
Units
µs
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T_JMAX, θ_JA, and the ambient temperature, T_A. The maximum
allowable power dissipation at any temperature is P_D = (T_JMAX − T_A)/θ_JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
T_JMAX = 125˚C (plastic) or 150˚C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80˚C/W. For the N
package, this number increases to 100˚C/W and for the V package this number is 120˚C/W.
Note 4: For current switching applications, both I_OUT1 and I_OUT2 must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degraded
by approximately V_OS ÷ V_REF. For example, if V_REF = 10V then a 1 mV offset, V_OS, on I_OUT1 or I_OUT2 will introduce an additional 0.01% linearity error.
Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 7: Guaranteed at V_REF=±10 V_DC and V_REF=±1 V_DC.
Note 8: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a
particular V_REF value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC0830 is “0.05% of FSR (MAX)”. This guarantees
that after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within 0.05%xV_REF of a
straight line which passes through zero and full scale.
Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only.
Note 10: A 100nA leakage current with R_fb=20k and V_REF=10V corresponds to a zero error of (100x10^−9x20x10³)x100/10 which is 0.02% of FS.
Note 11: The entire write pulse must occur within the valid data interval for the specified t_W, t_DS, t_DH, and t_S to apply.
Note 12: Typicals are at 25˚C and represent most likely parametric norm.
Note 13: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
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