CLC407 Datasheet, PDF (5/8 Pages) National Semiconductor (TI) – Low-Cost, Low-Power Programmable Gain Buffer with Disable

1
8
R
SMA
Input
Rin
50Ω
2
7
3
6
CLC407
4
5
Rout
SMA
50Ω
Output
Figure 1
Enable/Disable Operation Using ^+5V Supplies
The CLC407 has a TTL & CMOS logic compatible
disable function. Apply a logic low (i.e. < 0.8V) to pin
8, and the CLC407 is guaranteed disabled across its
temperature range. Apply a logic high to pin 8, (i.e. >
2.0V) and the CLC407 is guaranteed enabled. Voltage,
not current, at pin 8 determines the enable/disable
state of the CLC407.
Disable the CLC407 and its inputs and output become
high impedances. While disabled, the CLC407’s quies-
cent power drops to 8mW.
Use the CLC407’s disable to create analog switches or
multiplexers. Implement a single analog switch with
one CLC407 positioned between an input and output.
Create an analog multiplexer with several CLC407s.
Tie the outputs together and put a different signal on
each CLC407 input.
Operate the CLC407 without connecting pin 8. An
internal 20kΩ pull-up resistor guarantees the CLC407
is enabled when pin 8 is floating.
Enable/Disable Operation for Single or
Unbalanced Supply Operation
Supply 20kΩ
Mid-Point
Bias
Circuitry
20kΩ
Pin 7
+Vcc
Pull-up
Resistor
Vcc -Vee
Q2
2
20kΩ
Q1
I Tail
Pin 8
Disable
CLC407
Pin 4
-Vee
NOTE: Pins 4, 7, 8 are external
Figure 2
Input - Bias Current, Impedances, and Source
Termination Considerations
The CLC407 has:
• ^{a 6MΩ non-inverting input impedance.}
• ^{100nA non-inverting input bias current.}
If a large source impedance application is considered,
remove all parasitic capacitance around the non-invert-
ing input and source traces. Parasitic capacitances
near the input and source act as a low-pass filter and
reduce bandwidth.
Current feedback op amps have uncorrelated input
bias currents. These uncorrelated bias currents
prevent source impedance matching on each input
from cancelling offsets. Refer to application note
OA-07 of the data book to find specific circuits to
correct DC offsets.
Layout Considerations
Whenever questions about layout arise, USE THE
EVALUATION BOARD AS A TEMPLATE.
Use the 730013 and 730026 evaluation boards for the
DIP and SOIC respectively. These board layouts were
optimized to produce the typical performance of the
CLC407 shown in the data sheet. To reduce parasitic
capacitances, the ground plane was removed near
pins 2, 3, and 6. To reduce series inductance, trace
lengths of components and nodes were minimized.
Parasitics on traces degrade performance. Minimize
coupling from traces to both power and ground
planes. Use low inductance resistors for leaded
components .
Do not use dip sockets for the CLC407 DIP amplifiers.
These sockets can peak the frequency domain
response or create overshoot in the time domain
response. Use flush-mount socket pins if socketing
cannot be avoided. The 730013 circuit board device
holes are sized for Cambion P/N 450-2598 socket pins
or their functional equivalent.
Insert the back matching resistor R_out shown in
Figure 3 when driving coaxial cable or a capacitive
load. Use the plot in the typical performance section
labeled “Settling Time vs. Capacitive Load” to determine
the optimum resistor value for R_out for different capac-
itive loads. This optimal resistance improves settling
time for pulse-type applications and increases stability.
Figure 2 illustrates the internal enable/disable
operation of the CLC407. When pin 8 is left floating or
is tied to +V_cc, Q₁ is on and pulls tail current through
the CLC407 circuitry. When pin 8 is less than 0.8V
above the supply mid-point, Q₁ stops tail current from
flowing in the bias circuitry. The CLC407 is now disabled.
Disable Limitations
The internal feedback resistor, R_f limits off isolation in
inverting gain configurations. Do not apply voltages
greater than +V_cc or less than -V_ee to pin 8.
5
1
J1 = 0Ω
2
SMA
Input
Rin
50Ω
3
CLC407
4
C2
C4
0.1µfd 6.8µfd
8
7
C1
6 ^0.1µfd
Rout
5
50Ω
-5V
C3
6.8µfd
+5V
+
SMA
Output
+
Figure 3
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