ADC122S655 Datasheet, PDF (5/20 Pages) National Semiconductor (TI) – Dual 12-Bit, 200 kSPS to 500 kSPS, Simultaneous Sampling A/D Converter

Symbol
Parameter
Conditions
Typical Limits
Units
V_REF
Reference Voltage Range
DIGITAL INPUT CHARACTERISTICS
1.0
V (min)
V_A
V (max)
V_IH
Input High Voltage
V_IL
Input Low Voltage
I_IN
Input Current
C_IND
Input Capacitance
DIGITAL OUTPUT CHARACTERISTICS
V_IN = 0V or V_A
2.4
V (min)
0.8
V (max)
±1
µA (max)
2
4
pF (max)
V_OH
Output High Voltage
V_OL
Output Low Voltage
I_OZH, I_OZL
C_OUT
TRI-STATE Leakage Current
TRI-STATE Output Capacitance
Output Coding
I_SOURCE = 200 µA
I_SOURCE = 1 mA
I_SINK = 200 µA
I_SINK = 1 mA
Force 0V or V_A
Force 0V or V_A
V_A − 0.02
V_A − 0.09
0.01
V_A − 0.2
0.4
V (min)
V
V (max)
0.08
V
±1
µA (max)
2
4
pF (max)
Binary 2'S Complement
POWER SUPPLY CHARACTERISTICS
V_A
Analog Supply Voltage
4.5
V (min)
5.5
V (max)
I_VA (Conv)
Analog Supply Current, Continuously
Converting
f_SCLK = 16 MHz, f_S = 500 kSPS, f_IN = 20
kHz, V_A = 5V
2.2
I_VREF
(Conv)
Reference Current, Continuously
Converting
f_SCLK = 16 MHz, f_S = 500 kSPS, V_REF =
50
2.5V
2.75
mA (max)
60
µA (max)
I_VA (PD)
Analog Supply Current, Power Down
Mode (CS high)
f_SCLK = 16 MHz, V_A = 5.0V
f_SCLK = 0, V_A = 5.0V (Note 8)
I_VREF (PD)
Reference Current, Power Down Mode
(CS high)
f_SCLK = 16 MHz, V_REF = 2.5V
f_SCLK = 0, V_REF = 2.5V (Note 8)
PWR
(Conv)
Power Consumption, Continuously
Converting
f_SCLK = 16 MHz, f_S = 500 kSPS, f_IN = 20
kHz, V_A = 5.0V, V_REF = 2.5V
PWR
Power Consumption, Power Down Mode ^fSCLK ^{= 16 MHz, V}A ^{= 5.0V, V}REF ^{= 2.5V}
(PD)
(CS high)
f_SCLK = 0, V_A = 5.0V, V_REF = 2.5V
PSRR Power Supply Rejection Ratio
See the Specification Definitions for the
test condition
15
0.5
0.05
0.05
11.1
75
2.6
−85
µA
1.1
µA (max)
µA
0.1
µA (max)
13.9
mW (max)
µW
5.8
µW (max)
dB
AC ELECTRICAL CHARACTERISTICS
f_SCLK
f_SCLK
f_S
Maximum Clock Frequency
Minimum Clock Frequency
Maximum Sample Rate
Minimum Sample Rate
20
16
MHz (min)
1.6
6.4
MHz (max)
625
500
kSPS (min)
50
200
kSPS (min)
t_ACQ
t_CONV
t_AD
Track/Hold Acquisition Time
Conversion Time
Aperture Delay
3
SCLK cycles
12
SCLK cycles
6
ns
5
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