ADC08L060 Datasheet, PDF (5/19 Pages) National Semiconductor (TI) – 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal Sample-and-Hold

Converter Electrical Characteristics (Continued)
The following specifications apply for V_A = V_DR = +3.0V_DC, V_RT = +1.9V, V_RB = 0.3V, C_L = 10 pF, f_CLK = 60 MHz at 50% duty
cycle. Boldface limits apply for T_A = T_MIN to T_MAX: all other limits T_A = 25˚C (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
V_OH
High Level Output Voltage
V_OL
Low Level Output Voltage
DYNAMIC PERFORMANCE
V_A = V_DR = 2.7V, I_OH = −400 µA
V_A = V_DR = 2.7V, I_OL = 1.0 mA
2.6
2.4
V (min)
0.4
0.5
V (max)
ENOB Effective Number of Bits
SINAD Signal-to-Noise & Distortion
SNR
Signal-to-Noise Ratio
SFDR Spurious Free Dynamic Range
THD
Total Harmonic Distortion
HD2
2nd Harmonic Distortion
HD3
3rd Harmonic Distortion
IMD
Intermodulation Distortion
POWER SUPPLY CHARACTERISTICS
f_IN = 10.1 MHz, V_IN = FS − 0.25 dB
f_IN = 29 MHz, V_IN = FS − 0.25 dB
f_IN = 10.1 MHz, V_IN = FS − 0.25 dB
f_IN = 29 MHz, V_IN = FS − 0.25 dB
f_IN = 10.1 MHz, V_IN = FS − 0.25 dB
f_IN = 29 MHz, V_IN = FS − 0.25 dB
f_IN = 10.1 MHz, V_IN = FS − 0.25 dB
f_IN = 29 MHz, V_IN = FS − 0.25 dB
f_IN = 10.1 MHz, V_IN = FS − 0.25 dB
f_IN = 29 MHz, V_IN = FS − 0.25 dB
f_IN = 10.1 MHz, V_IN = FS − 0.25 dB
f_IN = 29 MHz, V_IN = FS − 0.25 dB
f_IN = 10.1 MHz, V_IN = FS − 0.25 dB
f_IN = 29 MHz, V_IN = FS − 0.25 dB
f₁ = 11 MHz, V_IN = FS − 6.25 dB
f₂ = 12 MHz, V_IN = FS − 6.25 dB
7.6
7.4
47.4
46.1
48
47.2
59.1
54.5
−56.9
−53.3
-61.1
−54.9
−64.2
−63.1
−55
6.9
43.3
44.5
Bits
Bits (min)
dB
dB (min)
dB
dB (min)
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
I_A
DRI_D
Analog Supply Current
Output Driver Supply Current
DC Input
f_IN = 10 MHz, V_IN = FS − 3 dB
DC Input
f_IN = 10 MHz, V_IN = FS − 3 dB
DC Input
13
15.9
mA (max)
14
mA
0.04
0.2
mA (max)
4.2
mA
13
16.1
I_A +
DRI_D
Total Operating Current
f_IN = 10 MHz, V_IN = FS − 3 dB, PD =
Low
CLK Low, PD = Hi
18.2
0.33
mA (max)
DC Input
39
48.3
mW (max)
PC
Power Consumption
f_IN = 10 MHz, V_IN = FS − 3 dB, PD =
53
mW
Low
CLK Low, PD = Hi
0.3
mW
FSE change with 2.7V to 3.3V change
PSRR₁ Power Supply Rejection Ratio
in V_A
−51
dB
PSRR₂ Power Supply Rejection Ratio
SNR with 200 mW at 1MHz on supply
45
dB
AC ELECTRICAL CHARACTERISTICS
f_C1
Maximum Conversion Rate
f_C2
Minimum Conversion Rate
t_CL
Minimum Clock Low Time
t_CH
Minimum Clock High Time
DC
Clock Duty Cycle
80
60
MHz (min)
10
MHz
0.62
ns (min)
0.62
ns (min)
5
%(min)
95
%(max)
t_OH
Output Hold Time
t_OD
Output Delay
CLK to Data Invalid
CLK to Data Transition
5.2
ns
5.0
ns (min)
7.1
9.4
ns (max)
Pipeline Delay (Latency)
5
Clock Cycles
t_AD
Sampling (Aperture) Delay
CLK Rise to Acquisition of Data
2.6
ns
5
www.national.com