ADC081000_09 Datasheet, PDF (5/30 Pages) National Semiconductor (TI) – High Performance, Low Power 8-Bit, 1 GSPS A/D Converter

Pin Functions
Pin No.
83
84
85
86
89
90
91
92
93
94
95
96
100
101
102
103
104
105
106
107
111
112
113
114
115
116
117
118
122
123
124
125
79
80
Symbol
D7-
D7+
D6-
D6+
D5-
D5+
D4-
D4+
D3-
D3+
D2-
D2+
D1-
D1+
D0-
D0+
Dd7-
Dd7+
Dd6-
Dd6+
Dd5-
Dd5+
Dd4-
Dd4+
Dd3-
Dd3+
Dd2-
Dd2+
Dd1-
Dd1+
Dd0-
Dd0+
OR+
OR-
82
81
2, 5, 8, 13, 16,
17, 20, 25, 28,
33, 128
40, 51, 62, 73,
88, 99, 110, 121
1, 6, 9, 12, 15,
21, 24, 27
42, 53, 64, 74,
87, 97, 108, 119
22, 23, 29, 34,
36 - 39,
41, 43 - 50, 52,
54 - 61, 63,
65 - 72,
75 - 78, 98, 109,
120
DCLK+
DCLK-
V_A
V_DR
GND
DR GND
NC
Equivalent Circuit
Description
LVDS data output bits sampled second in time sequence.
These outputs should always be terminated with a differential
100Ω resistance.
LVDS data output bits sampled first in time sequence. These
outputs should always be terminated with a differential
100Ω resistance.
Out of Range output. A differential high at these pins
indicates that the differential input is out of range (outside the
range of ±300 mV or ±400 mV as defined by the FSR pin).
See Section 1.6.
Differential Clock Outputs used to latch the output data.
Delayed and non-delayed data outputs are supplied
synchronous to this signal.
Analog power supply pins. Bypass these pins to GND.
Output Driver power supply pins. Bypass these pins to DR
GND.
Ground return for V_A
Ground return for V_DR
No Connection. Make no connection to these pins.
5
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